Patents by Inventor Shang-Chih Hsieh

Shang-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7797593
    Abstract: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: September 14, 2010
    Assignee: Faraday Technology Corp.
    Inventors: Chih-Chiang Hsu, Shang-Chih Hsieh
  • Publication number: 20100019774
    Abstract: An isolation cell having a test mode, connected between a first block and a second block, wherein the first block can operate in either a power-up mode or a power-down mode, comprises: an input terminal for receiving an input signal that is derived from the first block; an output terminal for outputting an output signal to the second block; a normal-sleep terminal for determining the isolation cell is operated in the power-up mode or in the power-down mode, and the logic level of the normal-sleep terminal is determined by the operation mode of the first block; and, a DFT-sleep terminal is for overwriting the logic level of the normal-sleep terminal when the isolation cell is in the test mode.
    Type: Application
    Filed: July 24, 2008
    Publication date: January 28, 2010
    Applicant: FARADAY TECHNOLOGY CORPORATION
    Inventors: Cheng-Chi WU, Yu-Wen TSAI, Shang-Chih HSIEH, Chun-Sung SU
  • Publication number: 20090251872
    Abstract: A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor.
    Type: Application
    Filed: April 8, 2008
    Publication date: October 8, 2009
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Chang-Yu Wu, Ming-Hsin Ku, Shang-Chih Hsieh, Hsin-Shih Wang
  • Publication number: 20090158104
    Abstract: A timing measurement circuit inside a memory chip delays balanced test signals for generating delayed test signals. Each of the delayed test signals is input a corresponding input pin of a memory subsystem of the memory chip. By adjusting delay amount of the delayed test signals, AC timing parameters of the memory subsystem are tested and measured. When the timing measurement circuit is in ring oscillation, a resolution thereof is measured.
    Type: Application
    Filed: December 18, 2007
    Publication date: June 18, 2009
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: Chih-Chiang Hsu, Shang-Chih Hsieh
  • Patent number: 7512856
    Abstract: The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled to a non-test data and a test data respectively, for selectively outputting the non-test data or the test data as the input data; a control circuit, coupled to a driving clock, for controlling the latch circuit to latch the input data as the output data according to the driving clock; and a scanning circuit, coupled to the driving clock and the latch circuit, for scanning the output data of the latch circuit to generate a scanning data according to the driving clock.
    Type: Grant
    Filed: November 22, 2006
    Date of Patent: March 31, 2009
    Assignee: Faraday Technology Corp.
    Inventors: Tzu-Pin Shen, Shang-Chih Hsieh
  • Publication number: 20080303573
    Abstract: A latch includes a data input terminal for receiving a data signal; a data output terminal for outputting the data signal; a first control terminal for receiving a control signal to set or reset the data signal derived from the data output terminal; a sleep signal input terminal for receiving a sleep signal to determine a sleep mode; a first logic circuit having input terminals coupled to the data input terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data output terminal; and a second logic circuit having input terminals coupled to the data output terminal, the first control terminal and the sleep signal input terminal and an output terminal coupled to the data input terminal; wherein the first logic circuit or the second logic circuit ignores the first control signal in response to the sleep signal when the latch is operated in the sleep mode.
    Type: Application
    Filed: June 11, 2007
    Publication date: December 11, 2008
    Applicant: FARADAY TECHNOLOGY CORPORATION
    Inventors: Shang-Chih Hsieh, Jeng-Huang Wu
  • Patent number: 7414458
    Abstract: A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: August 19, 2008
    Assignee: Faraday Technology Corp.
    Inventors: Jeng-Huang Wu, Yi-Hwa Chang, Shang-Chih Hsieh
  • Publication number: 20080116932
    Abstract: The present invention discloses a structured ASIC layout architecture, which includes a fixed body region and a programmable layout region. The fixed body region includes a tunnel wire or multiple tunnel wires for providing a function capability or multiple function capability. The programmable layout region is disposed on the fixed body region and is connected to the fixed body region, wherein the programmable layout region utilizes the tunnel wires of the fixed body region to propagate electrical signals.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 22, 2008
    Applicant: FARADAY TECHNOLOGY CORP.
    Inventors: CHANG-YU WU, MING-HSIN KU, SHANG-CHIH HSIEH, HSIN-SHIH WANG
  • Publication number: 20080116929
    Abstract: The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled to a non-test data and a test data respectively, for selectively outputting the non-test data or the test data as the input data; a control circuit, coupled to a driving clock, for controlling the latch circuit to latch the input data as the output data according to the driving clock; and a scanning circuit, coupled to the driving clock and the latch circuit, for scanning the output data of the latch circuit to generate a scanning data according to the driving clock.
    Type: Application
    Filed: November 22, 2006
    Publication date: May 22, 2008
    Inventors: Tzu-Pin Shen, Shang-Chih Hsieh
  • Publication number: 20070272947
    Abstract: A low power consuming semiconductor device comprises a p substrate, a first semiconductor cell formed over the p substrate, a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell, and a tap cell for coupling a power pin to n-well structures of the first semiconductor cell and the second semiconductor cell, and for coupling a ground pin to the p substrate. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.
    Type: Application
    Filed: May 10, 2006
    Publication date: November 29, 2007
    Inventors: Jeng-Huang Wu, Shang-Chih Hsieh, Yu-Wen Tsai
  • Publication number: 20070210857
    Abstract: A power gating circuit of a signal processing system includes a low dropout linear regulator, a control circuit, and an output circuit. The low dropout linear regulator includes a first transistor, an operational amplifier, a first resistor, a second resistor, and an output end. The output circuit includes a fourth transistor and a step-down circuit. The control circuit controls output voltage of the output circuit according to a control signal.
    Type: Application
    Filed: March 8, 2006
    Publication date: September 13, 2007
    Inventors: Jeng-Huang Wu, Yi-Hwa Chang, Shang-Chih Hsieh
  • Publication number: 20070090815
    Abstract: An integrated circuit with power gating function is disclosed, comprising a low dropout regulator coupled to a first power line to provide power to the first power line, a switch module connected between a second power line and a voltage source, turned on and off based on a mode signal to determine whether the voltage source provides power to the second power line, and an equalizer connected between the first and second power lines, activated with the switch module based on the mode signal to equalize the voltage of the second power line to that of the first power line when the mode signal permits the voltage source to provide power to the second power line.
    Type: Application
    Filed: October 24, 2005
    Publication date: April 26, 2007
    Inventor: Shang-Chih Hsieh