Patents by Inventor Shang-Chih Hsieh
Shang-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210297068Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.Type: ApplicationFiled: June 4, 2021Publication date: September 23, 2021Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
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Publication number: 20210294958Abstract: A logic circuit including first and second inverters, first and second NAND circuits, a transmission gate, and a transmission-gate-substitute (TGS) circuit, and wherein: for each of the first and second NAND circuits, a first input is configured to receive corresponding first and second data signals, and a second input is configured to receive an enable signal; the first inverter is configured to receive an output of the first NAND circuit; the transmission gate and the TGS circuit are arranged as a combination circuit which is configured to receive an output of the second NAND circuit as a data input, and outputs of the first inverter and the second NAND circuit as control inputs; the second inverter is configured to receive an output of the combination circuit; and an output of the second inverter represents one of an enable XOR (EXOR) function or an enable XNR (EXNR) function.Type: ApplicationFiled: June 7, 2021Publication date: September 23, 2021Inventors: Chi-Lin LIU, Jerry Chang-Jui KAO, Wei-Hsiang MA, Lee-Chung LU, Fong-Yuan CHANG, Sheng-Hsiung CHEN, Shang-Chih HSIEH
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Publication number: 20210273640Abstract: A circuit includes a level shifter circuit, an output circuit, an enable circuit, a first and a second feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to generate at least a first and a second signal responsive to at least the first enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, and configured to receive the first and the second signal. The enable circuit is configured to generate a second enable signal responsive to the first enable signal. The first feedback circuit is configured to receive the first enable signal, the second enable signal and the first feedback signal. The second feedback circuit is configured to receive the first enable signal, the second enable signal and the second feedback signal.Type: ApplicationFiled: May 17, 2021Publication date: September 2, 2021Inventors: Yu-Lun OU, Ji-Yung LIN, Yung-Chen CHIEN, Ruei-Wun SUN, Wei-Hsiang MA, Jerry Chang Jui KAO, Shang-Chih HSIEH, Lee-Chung LU
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Publication number: 20210265987Abstract: A circuit includes first and second power domains. The first power domain has a first power supply voltage level and includes a master latch, a first level shifter, and a slave latch coupled between the master latch and the first level shifter. The second power domain has a second power supply voltage level different from the first power supply voltage level and includes a retention latch coupled between the slave latch and the first level shifter, and the retention latch includes a second level shifter.Type: ApplicationFiled: May 7, 2021Publication date: August 26, 2021Inventors: Kai-Chi HUANG, Yung-Chen CHIEN, Chi-Lin LIU, Wei-Hsiang MA, Jerry Chang Jui KAO, Shang-Chih HSIEH, Lee-Chung LU
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Patent number: 11095272Abstract: An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop.Type: GrantFiled: August 9, 2019Date of Patent: August 17, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Yu Steve Wang, Chien-Te Wu, Shang-Chih Hsieh, Nick Tsai
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Publication number: 20210226628Abstract: An integrated circuit includes: a flip-flop circuit arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and a gating circuit coupled to the flip-flop circuit, for generating the first clock signal and the second clock signal according to the master signal and an input clock signal; wherein a first signal transition number of the first clock signal and a second signal transition number of the second clock signal are not greater than a third signal transition number of the input clock signal during the writing mode and the storing mode.Type: ApplicationFiled: January 16, 2020Publication date: July 22, 2021Inventors: GREG GRUBER, CHI-LIN LIU, MING-CHANG KUO, LEE-CHUNG LU, SHANG-CHIH HSIEH
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Patent number: 11063578Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.Type: GrantFiled: August 27, 2020Date of Patent: July 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun Ou, Wei-Chih Hsieh, Shang-Chih Hsieh
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Publication number: 20210203311Abstract: A circuit includes a multi-bit flip flop, an integrated clock gating circuit connected to the multi-bit flip flop, and a control circuit connected to the integrated clock gating circuit and the multi-bit flip flop. The control circuit compares output data of the multi-bit flip flop corresponding to input data with the input data. The control circuit generates an enable signal based on comparing the output data of the multi-bit flip flop corresponding to the input data with the input data of the multi-bit flip flop. The control circuit provides the enable signal to the integrated clock gating circuit, wherein the integrated clock gating circuit provides, based on the enable signal, a clock signal to the multi-bit flip flop causing the multi-bit flip flop to toggle.Type: ApplicationFiled: October 28, 2020Publication date: July 1, 2021Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Wei-Hsiang Ma
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Patent number: 11050415Abstract: In some embodiments, a flip-flop is disposed as an integrated circuit layout on a flip-flop region of a semiconductor substrate. The flip-flop includes a first clock inverter circuit that resides within the flip-flop region, and a second clock inverter circuit residing within the flip-flop region. The first clock inverter circuit and the second clock inverter circuit are disposed on a first line. Master switch circuitry is made up of a first plurality of devices which are circumscribed by a master switch perimeter that resides within the flip-flop region of the integrated circuit layout. The master switch circuitry and the first clock inverter circuit are disposed on a second line perpendicular to the first line. Slave switch circuitry is operably coupled to an output of the master switch circuitry. The slave switch circuitry is made up of a third plurality of devices that are circumscribed by a slave switch perimeter.Type: GrantFiled: November 25, 2019Date of Patent: June 29, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh, Che Min Huang
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Patent number: 11050423Abstract: An integrated circuit includes: a flip-flop circuit arranged to receive an input data for generating a master signal during a writing mode according to a first clock signal and a second clock signal, and to output an output data according to the first clock signal and the second clock signal during a storing mode; and a gating circuit coupled to the flip-flop circuit, for generating the first clock signal and the second clock signal according to the master signal and an input clock signal; wherein a first signal transition number of the first clock signal and a second signal transition number of the second clock signal are not greater than a third signal transition number of the input clock signal during the writing mode and the storing mode.Type: GrantFiled: January 16, 2020Date of Patent: June 29, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Greg Gruber, Chi-Lin Liu, Ming-Chang Kuo, Lee-Chung Lu, Shang-Chih Hsieh
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Patent number: 11030366Abstract: A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram; and selecting one group (selected group) of the recurrent ad hoc groups such that: the cells in the selected group have connections representing a corresponding logic circuit; each cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of a corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.Type: GrantFiled: May 12, 2020Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma
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Patent number: 11012073Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.Type: GrantFiled: July 22, 2020Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
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Patent number: 11012057Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.Type: GrantFiled: March 6, 2019Date of Patent: May 18, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Chi Huang, Jerry Chang Jui Kao, Chi-Lin Liu, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma, Yung-Chen Chien
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Publication number: 20210089698Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.Type: ApplicationFiled: December 2, 2020Publication date: March 25, 2021Inventors: Shang-Chih HSIEH, Chun-Fu CHEN, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Hsiang-Jen TSENG
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Publication number: 20200410152Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.Type: ApplicationFiled: September 15, 2020Publication date: December 31, 2020Inventors: CHIA HAO TU, HSUEH-CHIH CHOU, SANG HOO DHONG, JERRY CHANG JUI KAO, CHI-LIN LIU, CHENG-CHUNG LIN, SHANG-CHIH HSIEH
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Publication number: 20200395924Abstract: A device is disclosed and includes a first switch, a second switch, and a selector. The first switch outputs a first output signal at a first terminal thereof. The second switch is coupled to the first switch at a second terminal of the first switch. The second switch outputs a second output signal at the second terminal of the first switch in response to an input signal. The selector outputs, in response to the input signal received at two terminal of the selector, one of the first and second output signals as a third output signal. The third output signal has a logic value different from the input signal.Type: ApplicationFiled: August 27, 2020Publication date: December 17, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Lun OU, Wei-Chih HSIEH, Shang-Chih HSIEH
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Publication number: 20200395938Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.Type: ApplicationFiled: May 26, 2020Publication date: December 17, 2020Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
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Patent number: 10867099Abstract: An integrated circuit designing system includes a non-transitory storage medium, the non-transitory storage medium being encoded with a layout of a standard cell corresponding to a predetermined manufacturing process, the predetermined manufacturing process having a nominal minimum pitch of metal lines along a predetermined direction, the layout of the standard cell having a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The integrated circuit designing system further includes a hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.Type: GrantFiled: May 2, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
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Patent number: 10867100Abstract: An integrated circuit designing system includes a non-transitory storage medium encoded with a first set of standard cell layouts and a second set of standard cell layouts both being configured to perform a predetermined function. The predetermined manufacturing process having a nominal minimum pitch (T) of metal lines. Each standard cell layout of the first set of standard cell layouts and the second set of standard cell layouts having a cell height (H) wherein the cell height is a non-integral multiple of the nominal minimum pitch. A hardware processor communicatively is coupled with the non-transitory storage medium and is configured to execute a set of instructions for generating an integrated circuit layout based on the first set of standard cell layouts, the second set of standard cell layouts and the nominal minimum pitch; and creating a data file corresponding to the integrated circuit layout.Type: GrantFiled: July 10, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
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Publication number: 20200350916Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN