Patents by Inventor Shang-Chih Hsieh

Shang-Chih Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160134265
    Abstract: A flip-flop circuit includes a first latch, a second latch, and a trigger stage. The first latch is configured to set a first latch output signal based on a first latch input signal and a clock signal. The second latch is configured to set a second latch output signal based on a second latch input signal and the clock signal. The trigger stage is configured to generate the second latch input signal based on the first latch output signal. The trigger stage is configured to cause the second input signal to have different voltage swings based on the first latch output signal and the second latch output signal.
    Type: Application
    Filed: November 12, 2014
    Publication date: May 12, 2016
    Inventors: Chi-Lin LIU, Shang-Chih HSIEH, Lee-Chung LU, Chang-Yu WU
  • Publication number: 20160065184
    Abstract: A flip-flop circuit is provided. The flip-flop circuit includes a first latch, a trigger stage and a second latch. The first latch is configured to latch a selected signal in response to a first state of a clock signal, and provide a first output signal. The trigger stage, connected to the first latch, is configured to provide a trigger signal based on the clock signal and the first output signal. The second latch, connected to the trigger stage, is configured to latch the trigger signal in response to a second state of the clock signal, and provide a second output signal. The first state and the second state of the clock signal are complementary to each other.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 3, 2016
    Inventors: CHI-LIN LIU, SHANG-CHIH HSIEH, LEE-CHUNG LU, CHANG-YU WU
  • Patent number: 9245887
    Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Hui-Zhong Zhuang, Shang-Chih Hsieh, Li-Chun Tien
  • Patent number: 9203405
    Abstract: A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit. The clock trigger block is configured to output an output signal response to a clock signal received at the clock trigger block and the signal received from the logic circuit.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Lee-Chung Lu, Meng-Hsueh Wang, Chang-Yu Wu
  • Patent number: 9158877
    Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 13, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih Hsieh, Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng
  • Patent number: 9142630
    Abstract: Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: September 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co. Limited
    Inventors: Chang-Yu Wu, Chih-Chiang Chang, Shang-Chih Hsieh, Wei-Chih Hsieh
  • Publication number: 20150162910
    Abstract: A circuit includes a clock trigger block and a logic circuit. The logic circuit is configured to output a signal to the clock trigger block based on a logic level of an enable signal received at the logic circuit. The clock trigger block is configured to output an output signal response to a clock signal received at the clock trigger block and the signal received from the logic circuit.
    Type: Application
    Filed: May 15, 2014
    Publication date: June 11, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Lin LIU, Shang-Chih HSIEH, Lee-Chung LU, Meng-Hsueh WANG, Chang-Yu WU
  • Publication number: 20150035070
    Abstract: An integrated circuit layout includes a first active region, a second active region, a first PODE (poly on OD edge), a second PODE, a first transistor and a second transistor. The first transistor, on the first active region, includes a gate electrode, a source region and a drain region. The second transistor, on the second active region, includes a gate electrode, a source region and a drain region. The first active region and the second active region are adjacent and electrically disconnected with each other. The first PODE and the second PODE are on respective adjacent edges of the first active region and the second active region. The source regions of the first and second transistor are adjacent with the first PODE and the second PODE respectively. The first PODE and the second PODE are sandwiched between source regions of the first transistor and the second transistor.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Hui-Zhong Zhuang, Shang-Chih Hsieh, Li-Chun Tien
  • Publication number: 20140327471
    Abstract: An integrated circuit is manufactured by a predetermined manufacturing process having a nominal minimum pitch of metal lines. The integrated circuit includes a plurality of metal lines extending along a first direction and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines is separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. The plurality of standard cells includes a first standard cell configured to perform a predetermined function and having a first layout and a second standard cell configured to perform the predetermined function and having a second layout different than the first layout. The first and second standard cells have a cell height (H) along the second direction, and the cell height being a non-integral multiple of the nominal minimum pitch.
    Type: Application
    Filed: October 11, 2013
    Publication date: November 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Publication number: 20140327081
    Abstract: A semiconductor structure includes a first active area structure, an isolation structure surrounding the first active area structure, a first polysilicon structure, a first metal structure, and a second metal structure. The first polysilicon structure is over the first active area structure. The first metal structure is directly over a first portion of the first active area structure. The second metal structure is directly over and in contact with a portion of the first polysilicon structure and in contact with the first metal structure.
    Type: Application
    Filed: August 30, 2013
    Publication date: November 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Publication number: 20140327050
    Abstract: An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.
    Type: Application
    Filed: April 15, 2014
    Publication date: November 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shang-Chih HSIEH, Hui-Zhong ZHUANG, Ting-Wei CHIANG, Chun-Fu CHEN, Hsiang-Jen TSENG
  • Patent number: 8698205
    Abstract: An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: April 15, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiann-Tyng Tzeng, Chih-Liang Chen, Yi-Feng Chen, Kam-Tou Sio, Shang-Chih Hsieh, Helen Shu-Hui Chang
  • Patent number: 8667349
    Abstract: A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: March 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Chih Hsieh, Chih-Chiang Chang, Chang-Yu Wu
  • Publication number: 20140027821
    Abstract: Among other things, one or more techniques for enhancing device (e.g., transistor) performance are provided herein. In one embodiment, device performance is enhanced by forming an extended dummy region at an edge of a region of a device and forming an active region at a non-edge of the region. Limitations associated with semiconductor fabrication processing present in the extended dummy region more so than in non-edge regions. Accordingly, a device exhibiting enhanced performance is formed by connecting a gate to the active region, where the active region has a desired profile because it is comprised within a non-edge of the region. A dummy device (e.g., that may be less responsive) may be formed to include the extended dummy region, where the extended dummy region has a less than desired profile due to limitations associated with semiconductor fabrication processing, for example.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chang-Yu Wu, Chih-Chiang Chang, Shang-Chih Hsieh, Wei-Chih Hsieh
  • Publication number: 20130313615
    Abstract: An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.
    Type: Application
    Filed: May 25, 2012
    Publication date: November 28, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jiann-Tyng TZENG, Chih-Liang CHEN, Yi-Feng CHEN, Kam-Tou SIO, Shang-Chih HSIEH, Helen Shu-Hui CHANG
  • Patent number: 8552785
    Abstract: A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: October 8, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Zhang Kuo, Jen-Hang Yang, Shang-Chih Hsieh, Chih-Chiang Chang, Osamu Takahashi, Ta-Pen Guo, Sang Hoo Dong
  • Patent number: 8514000
    Abstract: Some embodiments relate to a flip-flop having a data input terminal, a data output terminal and a clock terminal. The flip-flop includes a master latch, a slave latch, and an isolation element coupled between the master latch output and slave latch. The isolation element is arranged to isolate capacitive loading seen by the output of the master latch that comes from the slave latch. In some embodiments, the master latch includes one or more drive enhancement elements on its feedforward and feedback paths. The slave latch can also include one or more drive enhancement elements on its feedforward and feedback paths. These drive enhancement elements, particularly in combination with the isolation element, may help to reduce the setup and hold times and enhance meta-stability resistance of the flip-flop relative to conventional implementations. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 20, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chih Hsieh, Shang-Chih Hsieh, Chih-Chiang Chang
  • Publication number: 20130113537
    Abstract: A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.
    Type: Application
    Filed: November 9, 2011
    Publication date: May 9, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Zhang KUO, Jen-Hang Yang, Shang-Chih Hsieh, Chih-Chiang Chang, Osamu Takahashi, Ta-Pen Guo, Sang Hoo Dong
  • Publication number: 20130042158
    Abstract: A scan-flip flop circuit includes an input stage for providing a data signal to a data node, wherein the input stage includes first and second stacks of transistors devices coupled to the data node. The first stack receives a data input signal during a normal operation mode for input to the data node, and the second stack receiving a scan input signal during a scan test mode for input to the data node. The scan flip-flop circuit also includes a master latch coupled directly to the data node for latching the data signal from the input stage and outputting the data signal; a slave latch coupled to an output of the master latch for latching the output from the master latch and outputting the output; and a scan and clock control logic module. The scan and clock control logic module controls the first stack to input the data input signal to the data node during normal operation mode.
    Type: Application
    Filed: August 11, 2011
    Publication date: February 14, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shang-Chih HSIEH, Chih-Chiang CHANG, Chang-Yu WU
  • Patent number: 8068349
    Abstract: A power supply architecture for a structural application-specific integrated circuit (ASIC) is provided. The power supply architecture includes a first conductor and a second conductor. The first conductor is coupled to a fixed voltage. The first conductor at least passes through two edges of a cell. The first conductor and the second conductor are connected through a contact. The second conductor at most passes through one edge of the cell. The structural ASIC includes a first metal layer and a second metal layer. The first metal layer includes the first conductor. The second metal layer includes the second conductor.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: November 29, 2011
    Assignee: Faraday Technology Corp.
    Inventors: Chang-Yu Wu, Ming-Hsin Ku, Shang-Chih Hsieh, Hsin-Shih Wang