Abstract: A method for setting parameters in design of a printed circuit board (PCB) includes obtaining multiple combinations of layout parameters of a PCB and inputting the multiple combinations of layout parameters into a predetermined PCB layout simulation software to obtain multiple interference parameter combinations. The multiple combinations of layout parameters and the multiple interference parameter combinations are defined as training samples, and a predetermined network model is trained through the training samples to obtain a first prediction model. The first prediction model is trained and tested to obtain an impedance prediction model. When the multiple combinations of layout parameters are inputted to the impedance prediction model, only an average predetermined error is allowed between impedance values predicted by the impedance prediction model and impedance values calculated by the predetermined PCB layout simulation software, to enable acceptance of that combination.

Abstract: An insole design method and an insole design system are provided, and the method includes: capturing an uncompressed free foot model by a depth camera and obtaining a free foot model three-dimensional image; capturing a pressed foot model stepped on a transparent pedal by the depth camera and obtaining a pressed foot model three-dimensional image; aligning the free foot model three-dimensional image with the pressed foot model three-dimensional image; calculating and obtaining a plantar deformation quantity according to the aligned free foot model three-dimensional image and the aligned pressed foot model three-dimensional image; and completing the designed insole according to a sole projection plane or a three-dimensional profile of the specific sole and the plantar deformation quantity.

Abstract: An optoelectronic package includes a carrier, a light emitting die, a cover, and an encapsulation material. The carrier has a carrying plane and a wiring layer on the carrying plane. The light emitting die is mounted on the carrying plane and electrically connected to the wiring layer. The cover is connected to carrier. A cavity is formed between the cover and the carrier, and the light emitting die is within the cavity. The encapsulation material formed on the carrier surrounds the cover. The encapsulation material completely covers the interface between the cover and carrier.

Abstract: A three-dimensional modeling method and a three-dimensional modeling system are provided.

Abstract: An automatic switching apparatus and an automatic switching method are disclosed. The automatic switching apparatus includes a universal serial bus Type-C input connector, a plurality of main links, at least one video output connector and at least one USB output connector. The automatic switching method includes the steps of: (a) detecting a use state of the plurality of main links; and (b) automatically switching the specification of the at least one USB output connector.

Abstract: An image synthesis method of a virtual object and the apparatus thereof are provided. The image synthesis method of the virtual object comprises providing a first depth image of a scene and a first two-dimensional image of the scene; providing a second depth image of the virtual object; adjusting a second depth value of the virtual object in the first depth image according to an objective location in the first depth image and a reference point of the second depth image; rendering a second two-dimensional image of the virtual object; and synthesizing the first two-dimensional image and the second two-dimensional image according to a lighting direction of the first two-dimensional image, an adjusted second depth value and the objective location in the first depth image.

Abstract: A three-dimensional modeling method and a three-dimensional modeling system are provided.

Abstract: A calibration method of a depth image capturing device including a projecting device and an image sensing device is provided. At least three groups of images of a calibration board having multiple feature points are captured. Intrinsic parameters of the image sensing device are calibrated according to the at least three groups of images. Multiple sets of coordinate values of corresponding points corresponding to the feature points in a projection pattern of the projecting device are obtained. Intrinsic parameters of the projecting device are obtained by calibration. Multiple sets of three-dimensional coordinate values of multiple feature points are obtained. An extrinsic parameter between the image sensing device and the projecting device is obtained according to multiple sets of three-dimensional coordinate values, the multiple sets of coordinate values of corresponding points, the intrinsic parameters of the image sensing device, and the intrinsic parameters of the projecting device.

Abstract: An optoelectronic package includes a wiring substrate having a holding plane, an optoelectronic chip, a reflective material, an optical element and an adhesive. The optoelectronic chip is mounted on the holding plane and electrically connected to the wiring substrate. The optoelectronic chip has an upper surface, a functional region and a side surface connected to the upper surface. The reflective material is on the holding plane and surrounds the optoelectronic chip. The reflective material covers the side surface and has an inclined surface. The inclined surface surrounds the upper surface and extends from an edge of the upper surface. The height of the reflective material at the inclined surface decreases from the optoelectronic chip toward a direction away from the optoelectronic chip. The adhesive covers the reflective material and the upper surface and is connected between the optoelectronic chip and the optical element.

Abstract: An optoelectronic package includes a substrate, a light emitting chip, an optical sealant, and an optical scattering layer. The substrate has a carrying plane and a wiring layer formed on the carrying plane. The light emitting chip used for emitting a light ray is mounted on the carrying plane and electrically connected to the wiring layer. The optical sealant covers the carrying plane and wraps the light emitting chip. The optical sealant is located in the path of the light ray. The optical scattering layer covers the optical sealant. The optical sealant located in the path of the light ray is formed between the substrate and the optical scattering layer. Preferably, the refractive index of the optical sealant is larger than or equal to the refractive index of the optical scattering layer.

Abstract: Provided are a method, system and computer readable medium for determining the base information in a predetermined area of a fetus genome, the method comprising following steps: constructing a sequence library for the DNA samples of the fetus genome; sequencing the sequence library to obtain the sequencing result of the fetus, the sequencing result of the fetus comprised of a plurality of sequencing data; and based on the sequencing result of the fetus, determining the base information in the predetermined area according to the hidden Markov model in conjunction with the genetic information of an individual related hereditarily to the fetus.

Abstract: A light emitting package base structure includes a carrier, a light emitting chip, a light transmission unit and a dam. The carrier has a supporting surface and an outer surface surrounding the supporting surface. The light emitting chip is disposed on the supporting surface and electrically connected to the carrier. The light transmission unit is disposed on the carrier and has a through hole. The dam is disposed between the carrier and the light transmission unit, and a hermetic receiving space is formed between the dam, the light transmission unit and the carrier. The light emitting chip is located in the hermetic receiving space and the dam has a side surface away from the hermetic receiving space. A gap is formed between the side surface and the outer surface, and the through hole is corresponded to a location between the side surface and the outer surface.

Abstract: An optoelectronic package includes a substrate, a light emitting chip, an optical sealant, and an optical scattering layer. The substrate has a carrying plane and a wiring layer formed on the carrying plane. The light emitting chip used for emitting a light ray is mounted on the carrying plane and electrically connected to the wiring layer. The optical sealant covers the carrying plane and wraps the light emitting chip. The optical sealant is located in the path of the light ray. The optical scattering layer covers the optical sealant. The optical sealant located in the path of the light ray is formed between the substrate and the optical scattering layer. Preferably, the refractive index of the optical sealant is larger than or equal to the refractive index of the optical scattering layer.

Abstract: A light emitting device includes a carrier, a light emitting chip, and a covering part disposed on the carrier. The carrier includes a board, a guiding metal layer, and a sealing material. The board has a first surface, a second surface, and a through vent that is divided into a first partial hole and a second partial hole. The first partial hole extends from the first surface to the second partial hole, and the second partial hole extends from the second surface to the first partial hole. The guiding metal layer is formed on the second surface and in the second partial hole, and covers the sidewall of the second partial hole. The guiding metal layer extends from the second partial hole to the second surface, and does not cover the sidewall of the first partial hole and the first surface. The sealing material seals the second partial hole.

Abstract: A light emitting device includes a carrier, a light emitting chip, and a covering part disposed on the carrier. The carrier includes a board, a guiding metal layer, and a sealing material. The board has a first surface, a second surface, and a through vent that is divided into a first partial hole and a second partial hole. The first partial hole extends from the first surface to the second partial hole, and the second partial hole extends from the second surface to the first partial hole. The guiding metal layer is formed on the second surface and in the second partial hole, and covers the sidewall of the second partial hole. The guiding metal layer extends from the second partial hole to the second surface, and does not cover the sidewall of the first partial hole and the first surface. The sealing material seals the second partial hole.

Abstract: An automatic switching apparatus and an automatic switching method are disclosed. The automatic switching apparatus includes a universal serial bus Type-C input connector, a plurality of main links, at least one video output connector and at least one USB output connector. The automatic switching method includes the steps of: (a) detecting a use state of the plurality of main links; and (b) automatically switching the specification of the at least one USB output connector.

Abstract: An image processing apparatus is disclosed. The splitter duplicates an original image signal into a first image signal and a second image signal. The first signal converter converts the second image signal having a first image format to the second image signal having a second image format. The image processor stores the second image signal in the memory according to an enable signal and continuously compares whether the current frame of the second image signal is the same as the previous frame of the second image signal. If they are different, the image processor continuously receives the second image signal and stores it in the memory. If they are the same, the image processor stops receiving the second image signal. The second converter converts the second image signal having the second image format to the second image signal having the first image format.

Abstract: A light emitting package base structure includes a carrier, a light emitting chip, a light transmission unit and a dam. The carrier has a supporting surface and an outer surface surrounding the supporting surface. The light emitting chip is disposed on the supporting surface and electrically connected to the carrier. The light transmission unit is disposed on the carrier and has a through hole. The dam is disposed between the carrier and the light transmission unit, and a hermetic receiving space is formed between the dam, the light transmission unit and the carrier. The light emitting chip is located in the hermetic receiving space and the dam has a side surface away from the hermetic receiving space. A gap is formed between the side surface and the outer surface, and the through hole is corresponded to a location between the side surface and the outer surface.

Abstract: An optoelectronic package includes a carrier, a light emitting die, a cover, and an encapsulation material. The carrier has a carrying plane and a wiring layer on the carrying plane. The light emitting die is mounted on the carrying plan and electrically connected to the wiring layer. The cover is connected to carrier. A cavity is formed between the cover and the carrier, and the light emitting die is within the cavity. The encapsulation material formed on the carrier surrounds the cover. The encapsulation material completely covers the interface between the cover and carrier.

Abstract: A footwear has an outsole and a vamp connected to the outsole. The vamp includes at least one patch and the outsole includes at least one patch located adjacent to the patch of the vamp. The patch of the vamp is made with a color/color pattern different from that of the vamp and the outsole. The patch of the outsole is made with a color/color pattern different from that of the outsole and the vamp. The patches may be made with a same color/color pattern.