Patents by Inventor Shang Yi

Shang Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9059384
    Abstract: LED packaging construction includes a substrate, a cavernous construction, a LED, and a reflection layer. The substrate is daubed with an insulation layer and a circuit layer on a surface on the substrate, wherein the substrate is made of metal, and the insulation layer is disposed between the circuit layer and the substrate. The cavernous construction is disposed on the substrate and surrounds the LED, and is formed by disposing a photoresist layer and patterning the photoresist layer. The circuit layer electrically connects the LED through a conducting wire. The reflection layer is at least disposed on a first surface of the cavernous construction, wherein the first surface surrounds the LED and faces toward the LED, and a part of light emitted from the LED is reflected by the reflection layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 16, 2015
    Assignee: Unistars
    Inventors: Shin-Shien Shie, Tien-hao Huang, Shang-Yi Wu, Yi-chun Wu
  • Publication number: 20150143957
    Abstract: A watch winder case is disclosed to include two opposite end plates connected to each other through two first support bars and two second support bars. Two first side plates are respectively abutted and inserted between one of the two first support bars and one of the two second support bars, and a second side plate is abutted and inserted between the two second support bars. Thus, the structural strength and structural stability of the watch winder case can be enhanced.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Applicant: Gooten Innolife Corporation
    Inventors: Yi-Wei LIAO, Shang-Yi LIU
  • Publication number: 20150105264
    Abstract: Provided are a method and a system for identifying whether the twins are dizygotic twins, the method comprising: typing at least one polymorphic loci of the twins fetuses to obtain the fetal polymorphism types, comparing the fetal polymorphism types with the corresponding polymorphism types of their parents, determining whether the twins are dizygotic twins on the basis of the comparison result.
    Type: Application
    Filed: May 23, 2012
    Publication date: April 16, 2015
    Applicant: BGI DIAGNOSIS CO., LTD.
    Inventors: Huijuan Ge, Jing Zheng, Shang Yi, Xuchao Li, Jian Wang, Jun Wang, Huanming Yang, Xiuqing Zhang
  • Publication number: 20150094210
    Abstract: Provided are a method, system and computer readable medium for determining the base information in a predetermined area of a fetus genome, the method comprising following steps: constructing a sequence library for the DNA samples of the fetus genome; sequencing the sequence library to obtain the sequencing result of the fetus, the sequencing result of the fetus comprised of a plurality of sequencing data; and based on the sequencing result of the fetus, determining the base information in the predetermined area according to the hidden Markov model in conjunction with the genetic information of an individual related hereditarily to the fetus.
    Type: Application
    Filed: May 14, 2012
    Publication date: April 2, 2015
    Applicant: BGI DIAGNOSIS CO., LTD.
    Inventors: Shengpei Chen, Huijuan Ge, Xuchao Li, Shang Yi, Jian Wang, Jun Wang, Huanming Yang, Xiuqing Zhang
  • Publication number: 20150060911
    Abstract: An optoelectronic semiconductor device comprises a substrate, at least one solid via plug, at least one optoelectronic semiconductor chip, a phosphor layer and a molding body. The at least one solid via plug penetrates through the substrate. The at least one optoelectronic semiconductor chip has a first electrode aligned to and electrically connected with the solid via plug. The phosphor layer covers at least one surface of the optoelectronic semiconductor chip. The molding body encapsulates the substrate, the optoelectronic semiconductor chip and the phosphor layer. The number of solid valid plugs, substrate surfaces, electrodes, bonding pad on each surface of the substrate for forming each optoelectronic semiconductor device can be, for example, two, respectively.
    Type: Application
    Filed: September 5, 2013
    Publication date: March 5, 2015
    Applicant: Unistars Corporation
    Inventors: Wen-Cheng CHIEN, Tien-Hao HUANG, Shang-Yi WU
  • Publication number: 20140365972
    Abstract: A method for selecting multiple objects and an electronic device are provided, and the method for selecting multiple objects is applicable to the electronic device. The electronic device includes a touch screen and a processor, and the processor executes an operating system (OS). The method includes: identifying whether an application currently executed by the OS belongs to a first type application or a second type application; when the application currently executed by the OS is identified to belong to the first type application, displaying a first multi-selection button by the touch screen, where the first multi-selection button is configured to generate a first button event when the first multi-selection button is triggered ; and when the first button event is detected by the touch screen, activating or deactivating a first multiple objects selection function of the application which is currently executed by the OS.
    Type: Application
    Filed: February 26, 2014
    Publication date: December 11, 2014
    Applicant: Acer Incorporated
    Inventors: Chien-Hung Li, Chan-Ping Po, Yueh-Yarng Tsai, Yu-Hsuan Shen, Shang-Yi Huang, Yi-Wen Liu
  • Patent number: 8878780
    Abstract: A display apparatus including an image generator, a projection lens set, a depth detecting module detecting the position of user, and a control unit is provided, wherein the control unit is electrically connected to the image generator, the projection lens set and the depth detecting module. An image displayed by the image generator is projected through the projection lens set and generates a floating real image between the projection lens set and the user. Each beam forming the floating real image has a light-cone angle ?. The image generator and the projection lens adjust the position of the floating real image according to the position of user. The size of the floating real image is L, the distance between two eyes of the user is W, the distance between the user and the floating real image is D, and the light-cone angle ? satisfies the formula of ? ? tan - 1 ? ( L + W D ) .
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: November 4, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Yi-Jen Chan, Golden Tiao, Chang-Ying Chen, Chy-Lin Wang, Kun-Lung Tseng, Shang-Yi Lin
  • Publication number: 20140325465
    Abstract: A chip with flexible pad sequence manipulation is provided. The chip can be a memory controller, and includes a hub unit. The hub unit, formed by a gate array, is placed in a hub region predetermined during placing and routing procedures, and is capable of supporting re-placing and re-routing for changing interior interconnections and a pad sequence of the chip.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 30, 2014
    Applicant: MStar Semiconductor, Inc.
    Inventors: Hsin-Cheng Lai, Yung Chang, Chen-Nan Lin, Chung-Ching Chen, Chen-Hsing Lo, Shang-Yi Chen, Cheng-Hsun Liu
  • Patent number: 8866313
    Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 21, 2014
    Assignee: Unistars Corporation
    Inventors: Tien-Hao Huang, Hsin-Hsie Lee, Yi-Chun Wu, Shang-Yi Wu
  • Patent number: 8866268
    Abstract: A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: October 21, 2014
    Assignee: Unistars Corporation
    Inventors: Shang-Yi Wu, Wen-Cheng Chien, Chia-Lun Tsai, Tien-Hao Huang
  • Publication number: 20140247585
    Abstract: A semiconductor lighting apparatus includes an illumination module and a power module. The illumination module includes a supporting member, a semiconductor light-emitting element, an electrode structure and a first connecting member. The semiconductor light-emitting element is mounted on the supporting member and electrically connected with the electrode structure. The first connecting member is mounted on a first side of the supporting member. The power module is configured to connect to the first side of the supporting member, and includes a second connecting member and a driving circuit member. The second connecting member is detachably connected with the first connecting member. The driving circuit member is electrically connected with the second connecting member and electrically connected with the electrode structure to provide a driving power to the semiconductor light-emitting element.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Applicant: UNISTARS CORPORATION
    Inventors: Wen-Cheng CHIEN, Shang-Yi WU, Shin-Shien SHIE
  • Patent number: 8778707
    Abstract: A method for fabricating a silicon submount for LED packaging. A silicon substrate is provided. A reflection layer is formed on the silicon substrate. Portions of the reflection layer and the silicon substrate are removed to form openings. A wafer backside grinding process is carried out to thin the silicon substrate thereby turning the openings into through silicon vias. An insulating layer is then deposited to cover the reflection layer and the silicon substrate. A seed layer is formed on the insulating layer. A resist pattern is then formed on the seed layer. A metal layer is formed on the seed layer not covered by the resist pattern. The resist pattern is then stripped. The seed layer not covered by the metal layer is then removed.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: July 15, 2014
    Assignee: Xintec Inc.
    Inventors: Shang-Yi Wu, Chien-Hui Chen
  • Publication number: 20140191274
    Abstract: A substrate includes a die-bonding zone and a glue spreading pattern. The die-bonding zone is set to bond a die. The glue spreading pattern is placed in the die-bonding zone and includes a containing space. The die is placed on the glue spreading pattern, an area of a bottom of the die is greater than an area of an opening of the glue spreading pattern, the containing room of the glue spreading pattern is filled with a glue, and the die is bonded to the substrate by means of the glue.
    Type: Application
    Filed: March 13, 2013
    Publication date: July 10, 2014
    Applicant: Unistars Corporation
    Inventors: Tien-Hao Huang, Hsin-Hsie Lee, Yi-Chun Wu, Shang-Yi Wu
  • Publication number: 20140176676
    Abstract: The disclosure provides a stereo display system including a stereo display, a depth detector, and a computing processor. The stereo display displays a left eye image and a right eye image, such that a left eye and a right eye of a viewer generate a parallax to view a stereo image. The depth detector captures a depth data of a three-dimensional space. The computing processor controls image display of the stereo display. The computing processor analyzes an eyes position of the viewer according to the depth data, and when the viewer moves horizontally, vertically, or obliquely in the three-dimensional space relative to the stereo display, the computing processor adjusts the left eye image and the right eye image based on variations of the eyes position. Furthermore, an image interaction system, a method for detecting finger position, and a control method of stereo display are also provided.
    Type: Application
    Filed: September 30, 2013
    Publication date: June 26, 2014
    Applicant: Industrial Technology Research Institue
    Inventors: Shang-Yi Lin, Tien-You Lee, Chia-Chen Chen
  • Publication number: 20140151730
    Abstract: LED packaging construction includes a substrate, a cavernous construction, a LED, and a reflection layer. The substrate is daubed with an insulation layer and a circuit layer on a surface on the substrate, wherein the substrate is made of metal, and the insulation layer is disposed between the circuit layer and the substrate. The cavernous construction is disposed on the substrate and surrounds the LED, and is formed by disposing a photoresist layer and patterning the photoresist layer. The circuit layer electrically connects the LED through a conducting wire. The reflection layer is at least disposed on a first surface of the cavernous construction, wherein the first surface surrounds the LED and faces toward the LED, and a part of light emitted from the LED is reflected by the reflection layer.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 5, 2014
    Applicant: Unistars
    Inventors: Shin-Shien Shie, Tien-hao Huang, Shang-Yi Wu, Yi-chun Wu
  • Publication number: 20140151741
    Abstract: A semiconductor structure and its manufacturing method including multiple steps are provided. First, a patterned circuit board having a substrate and a patterned circuit layer is provided. The substrate includes a first surface, a second surface, at least one connecting channel, and at least one conductive through hole, wherein patterned circuit layer is disposed on the first surface, a second surface, and the inside wall of the conductive through hole. Then, the patterned circuit board is disposed on a carrier, and the patterned circuit layer disposed on one of the first surface and the second surface is touched with the carrier. Then, a filling process is applied. A filling material flows to the conductive through hole via the first surface or the second surface from the connecting channel. Then, a package material is provided to produce a semiconductor structure.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 5, 2014
    Applicant: Unistars
    Inventors: Tien-hao Huang, Shang-Yi Wu, Yi-chun Wu
  • Publication number: 20140137065
    Abstract: An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites.
    Type: Application
    Filed: January 20, 2014
    Publication date: May 15, 2014
    Applicant: MEDIATEK INC.
    Inventors: Huai-Yuan Feng, Ching-Gu Pan, Yan-Bin Luo, Hua Wu, Shang-Yi Lin
  • Patent number: 8665606
    Abstract: An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: March 4, 2014
    Assignee: Mediatek Inc.
    Inventors: Huai-Yuan Feng, Ching-Gu Pan, Yan-Bin Luo, Hua Wu, Shang-Yi Lin
  • Patent number: 8647644
    Abstract: The invention provides an article having a mesoporous silicate matrix, such as a particle, having one or more pores; and one or more releasable caps obstructing one or more of the pores for delivery of one or more agents to plant cells or other chlorophyll containing cells, or fungi.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: February 11, 2014
    Assignee: Iowa State University Research Foundation, Inc.
    Inventors: Francois Jean George Torney, Kan Wang, Victor Shang-Yi Lin, Brian G. Trewyn, Supratim Giri
  • Publication number: 20140017828
    Abstract: A method for fabricating a silicon submount for LED packaging. A silicon substrate is provided. A reflection layer is formed on the silicon substrate. Portions of the reflection layer and the silicon substrate are removed to form openings. A wafer backside grinding process is carried out to thin the silicon substrate thereby turning the openings into through silicon vias. An insulating layer is then deposited to cover the reflection layer and the silicon substrate. A seed layer is formed on the insulating layer. A resist pattern is then formed on the seed layer. A metal layer is formed on the seed layer not covered by the resist pattern. The resist pattern is then stripped. The seed layer not covered by the metal layer is then removed.
    Type: Application
    Filed: September 11, 2013
    Publication date: January 16, 2014
    Applicant: XINTEC INC.
    Inventors: Shang-Yi WU, Chien-Hui CHEN