Patents by Inventor Shawn Hall

Shawn Hall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • POWER CONVERTER USING NEAR-LOAD OUTPUT CAPACITANCE, DIRECT INDUCTOR CONTACT, AND/OR REMOTE CURRENT SENSE
    Publication number: 20170194871
    Abstract: An apparatus includes a first circuit board including first components including a load, and a second circuit board including second components including switching power devices and an output inductor. Ground and output voltage contacts between the circuit boards are made through soldered or connectorized interfaces. Certain components on the first circuit board and certain components, including the output inductor, on the second circuit board act as a DC-DC voltage converter for the load. An output capacitance for the conversion is on the first circuit board with no board-to-board interface between the output capacitance and the load. The inductance of the board-to-board interface functions as part of the output inductor's inductance and not as a parasitic inductance. Sense components for sensing current through the output inductor are located on the first circuit board. Parasitic inductance of the board-to-board interface has less effect on a sense signal provided to a controller.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Paul W. Coteus, Andrew Ferencz, Shawn A. Hall, Todd E. Takken, Shurong Tian, Xin Zhang
  • HIGH-DENSITY, FAIL-IN-PLACE SWITCHES FOR COMPUTER AND DATA NETWORKS
    Publication number: 20170155598
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • WATER-ASSISTED AIR COOLING FOR A ROW OF CABINETS
    Publication number: 20170135245
    Abstract: A cooling apparatus and method including a plurality of heat-producing devices positioned in a plurality of cabinets arranged in a row that allows flow of a first fluid through the heat-producing devices and cabinets where the flow is directed from an upstream end of the row to a downstream end of the row. The cabinets have a space therebetween wherein a heat exchanger is positioned between and adjacent to the cabinets, thereby the cabinets and heat exchangers alternate in the row. Each heat exchanger allows flow of a second fluid therethrough for cooling the first fluid. A fluid-moving device is positioned adjacent the heat-producing devices for encouraging flow of the first fluid through the cabinets' heat-producing devices and through the heat exchangers, thereby encouraging heat transfer in each of the heat exchangers from the first fluid to the second fluid.
    Type: Application
    Filed: February 11, 2013
    Publication date: May 11, 2017
    Applicant: International Business Machines Corporation
    Inventor: Shawn Hall
  • High-density, fail-in-place switches for computer and data networks
    Patent number: 9634959
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • FLEXIBLE COLD PLATE WITH ENHANCED FLEXIBILITY
    Publication number: 20160290728
    Abstract: An apparatus for cooling an electronic component has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The joined planar top and bottom members have a sidewall structure of reduced height (and generally the height of the cold plate) between active areas in order to improve flexibility. The stiffness of the sidewalls is reduced by very advantageously reduce the height of the sidewalls. In one embodiment, the sidewalls are shorter in height corresponding to regions only between active areas. Alternatively, the sidewalls are of reduced height everywhere by insetting the active areas within the top and/or bottom sheets.
    Type: Application
    Filed: August 4, 2015
    Publication date: October 6, 2016
    Inventors: Paul W. Coteus, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • BURST RESISTANT THIN WALL HEAT SINK
    Publication number: 20160290727
    Abstract: An apparatus for cooling an electronic component has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The planar top member has a plurality of stamped indent formations at a plurality of locations, each indent formation providing a contact surface such that the planar top member is affixed to the bottom member by braze or solder at each contact surface. Alternatively, the planar bottom member also has a plurality of stamped indent formations in alignment with indent formations of the top member. The planar top member is affixed to the bottom member by brazing or soldering each respective contact surface of an indent formation of the planar top member to an opposing contact surface of a corresponding indent formation of the parallel planar bottom member.
    Type: Application
    Filed: August 4, 2015
    Publication date: October 6, 2016
    Inventors: Paul W. Coteus, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • Memory system connector
    Patent number: 9298395
    Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Paul W. Coteus, Shawn A. Hall, Hillery C. Hunter, Douglas J. Joseph, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Todd E. Takken
  • Device Account Upgrade-At-Claim
    Publication number: 20160078553
    Abstract: A method of upgrading a device account is provided, the method comprising: disposing a processor in communication with a software package, wherein said software package is capable of receiving a data file containing a current device account status indicator from a device account status data provider; referencing said data file to inform a decision regarding whether a device account owner is eligible for an account upgrade at the time a device account claim is processed; and notifying said owner whether a device protection account upgrade is available.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Applicant: ASURION, LLC
    Inventors: Jeff Kulla, Shawn Hall
  • Implementing inverted master-slave 3D semiconductor stack
    Patent number: 9281302
    Abstract: A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Shawn A. Hall, Todd E. Takken
  • Mechanical linkage for lifting
    Patent number: 9266704
    Abstract: A “hex-plus-X” linkage for lifting applications, comprising a hexagonal assembly, an X assembly, and actuation means. The hexagonal assembly comprises six bars, B1 through B6, pivotally attached end-to-end in a closed hexagonal loop, B1-B2-B3-B4-B5-B6-B1. B1 is a base bar; B4 is a top bar. The X assembly, comprising two bars B7 and B8 pivotally attached to each other, is pivotally and slidably attached to B1 and B4, thereby eliminating two unwanted degrees of freedom from the hexagonal assembly without limiting the size of B1 or B4. The actuation means is pivotally attached at knee joints between B2-B3 and B5-B6. To save space and eliminate tripping hazards, the knee joints are concave, so that B2-B3 and B5-B6 do not protrude. When actuated, the linkage lifts a load by modulating a distance between B1 and B4. Mechanical advantage is high. Slidable joints bear modest loads, minimizing wear. None of B4 is cantilevered.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: February 23, 2016
    Inventor: Shawn A Hall
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20160011996
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Application
    Filed: April 30, 2015
    Publication date: January 14, 2016
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • HIGH-DENSITY, FAIL-IN-PLACE SWITCHES FOR COMPUTER AND DATA NETWORKS
    Publication number: 20150289406
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Application
    Filed: November 20, 2014
    Publication date: October 8, 2015
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • SUBTERRANEAN HYDRAULIC SECURITY SYSTEM AND METHOD OF USE
    Publication number: 20150252608
    Abstract: In one embodiment, a subterranean hydraulic security system comprises a safe, support legs, and a lifting means, such as a hydraulic scissor lift and a pump, a screw jack, or other equivalent means. The underground safe system may also comprise an oversized upper portion formed from concrete, wood, or other rigid material. In another embodiment, a subterranean hydraulic security system comprises a gate, securing posts, and a lifting means.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 10, 2015
    Inventors: Michael Shawn Hall, Jason Neil Hall
  • IMPLEMENTING INVERTED MASTER-SLAVE 3D SEMICONDUCTOR STACK
    Publication number: 20150236001
    Abstract: A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 20, 2015
    Applicant: International Business Machines Corporation
    Inventors: Paul W. Coteus, Shawn A. Hall, Todd E. Takken
  • IMPLEMENTING INVERTED MASTER-SLAVE 3D SEMICONDUCTOR STACK
    Publication number: 20150236004
    Abstract: A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
    Type: Application
    Filed: April 29, 2015
    Publication date: August 20, 2015
    Inventors: Paul W. Coteus, Shawn A. Hall, Todd E. Takken
  • Multi-petascale highly efficient parallel supercomputer
    Patent number: 9081501
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: July 14, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Thermal Interface Solution With Reduced Adhesion Force
    Publication number: 20150092352
    Abstract: An article of manufacture comprises a composite, layered, and compressible TIM differentially adhered to a heat-spreader surface and a heat-source surface, such as a circuit card, where at least one of the surfaces comprises an uneven surface, and the TIM is compressively bonded to the uneven surface. The adhesive strength of the TIM to the heat-spreader surface is unequal to the adhesive strength of the TIM to the heat-source surface, and is adjusted so that the heat-spreader surface and the heat-source surface can be separated without damaging the heat-source surface. A process comprises manufacturing the article of manufacture.
    Type: Application
    Filed: September 29, 2013
    Publication date: April 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Timothy J. Chainer, Paul W. Croteus, Michael Gaynes, Shawn Hall, Shurong Tian
  • WATER-ASSISTED AIR COOLING FOR A ROW OF CABINETS
    Publication number: 20140223946
    Abstract: A cooling apparatus and method including a plurality of heat-producing devices positioned in a plurality of cabinets arranged in a row that allows flow of a first fluid through the heat-producing devices and cabinets where the flow is directed from an upstream end of the row to a downstream end of the row. The cabinets have a space therebetween wherein a heat exchanger is positioned between and adjacent to the cabinets, thereby the cabinets and heat exchangers alternate in the row. Each heat exchanger allows flow of a second fluid therethrough for cooling the first fluid. A fluid-moving device is positioned adjacent the heat-producing devices for encouraging flow of the first fluid through the cabinets' heat-producing devices and through the heat exchangers, thereby encouraging heat transfer in each of the heat exchangers from the first fluid to the second fluid.
    Type: Application
    Filed: February 11, 2013
    Publication date: August 14, 2014
    Applicant: International Business Machines Corporation
    Inventor: Shawn Hall
  • Establishing parse scope
    Patent number: 8799244
    Abstract: Example apparatus, methods, and computers control establishing a shared parse scope between two computers that intend to be involved in a shared de-duplication action. One example method includes, upon determining that a first de-duplication logic and a second de-duplication logic are to participate in a shared de-duplication action for an object, controlling the first de-duplication logic to establish a shared parse scope with the second de-duplication logic. Establishing the shared parse scope may include negotiations between the computers, where the negotiations transfer dialect information. The dialect information may take the form of rules. The method may also include persisting the shared parse scope.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: August 5, 2014
    Inventors: Jeffrey Vincent Tofano, Shawn Hall
  • MEMORY SYSTEM CONNECTOR
    Publication number: 20140115281
    Abstract: According to one embodiment a memory system includes a circuit card and a separable area array connector on the circuit card. The system also includes a memory device positioned on the circuit card, wherein the memory device is configured to communicate with a main processor of a computer system via the area array connector.
    Type: Application
    Filed: October 22, 2012
    Publication date: April 24, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Paul W. Coteus, Shawn A. Hall, Hillery C. Hunter, Douglas J. Joseph, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Todd E. Takken