Abstract: Gate-all-around transistor devices and methods for manufacturing the same are provided. The semiconductor device includes a substrate. The substrate includes a plurality of isolation regions formed in the substrate, the plurality of isolation regions comprising an isolation material. The substrate further includes a buffer region formed in the substrate, the buffer region separating adjacent isolation regions. The semiconductor device further includes a plurality of fins, each fin formed on a corresponding isolation region of the plurality of isolation regions. Each fin includes a buffer layer contacting the isolation material and a plurality of silicon layers and a plurality of silicon germanium layers alternatingly arranged in a plurality of stacked pairs on the buffer layer.

Abstract: Embodiments of the present disclosure generally relate to the field of semiconductor manufacturing processes, more particularly, to precursor chemistries and methods of depositing silicon-containing films for forming semiconductor devices. In one or more embodiments, a method includes co-flowing a silicon-containing precursor with a dopant precursor into a processing chamber at a temperature of 600° C. or less to deposit an epitaxial layer over a substrate disposed within the processing chamber. The silicon-containing precursor is selected from a list consisting of silane (SiH4), disilane (Si2H6), trisilane(Si3H8), tetrasilane (Si4H10), monochlorotrisilane (Si3H7Cl), diiodosilane (SiH2I2), and dibromosilane (SiH2Br2).

Abstract: A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surfaces of the semiconductor structure, (c) a recrystallization anneal process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench, (d) an etch process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process, to epitaxially form a source/drain region over the silicon-containing crystalline layer wi

Abstract: Embodiments of the present disclosure generally relate to plasma generator and injector assembly for use in a processing chamber. In one or more embodiments, a substrate processing chamber includes a chamber body at least partially defining an internal volume. The processing chamber further includes a plasma generator including a first housing to deliver a generation power and a second housing coupled to the first housing to at least partially define a plasma volume between the second housing and the first housing. A gas inlet extends through the second housing to the plasma volume. The gas inlet is configured to be fluidly coupled to a gas source. An injector is fluidly connected to the plasma generator. The injector includes one or more openings arranged in one or more channels. A mount arm includes a first end section coupled to the injector and a second end section coupled to the second housing.

Abstract: A susceptor for processing a substrate is provided including a base and a coating formed over the base. The base includes an outer rim having an inner edge, an outer edge, and a top connecting the inner edge to the outer edge; and an inner dish disposed inside the outer rim and coupled to the outer rim, the inner dish recessed from the top of the outer rim, the inner dish having a front side and an opposing back side. The coating has an outer surface that includes a first portion formed over the front side of the inner dish. The first portion of the outer surface of the coating includes a first region and a second region, the first region has a first average level of roughness, the second region has a second average level of roughness.

Abstract: Superlattice structures that may be used in gate-all around (GAA) transistor devices and methods for manufacturing the same are provided. In one or more implementations of the present disclosure, carbon-containing precursors are used to dose the SiGe surface prior to silicon channel growth to suppress germanium diffusion. The carbon-containing precursors can be selected from organosilane precursors, organogermane precursors, and carbon precursors. The carbon-containing precursor can be used with chlorinated precursors. The carbon-containing precursor can be flowed throughout the growth of the entire SiGe thickness. The carbon-containing precursor can be flowed toward the end of the growth of the SiGe thickness. The carbon-containing precursor can be flowed after growth of the SiGe thickness.

Abstract: The present disclosure relates to UV light sources and/or processing activation in processing chambers, and related apparatus and methods. In one or more embodiments, a processing chamber applicable for semiconductor manufacturing includes a chamber body and a lid. The lid and the chamber body at least partially define an internal volume. The processing chamber further includes a substrate support disposed in a processing volume of the internal volume and a gas inlet fluidly coupled to the chamber body to provide gas to the internal volume. The gas inlet includes one or more UV energy sources for irradiating gas within the inlet prior to the gas entering the processing volume. The one or more UV energy sources comprise a first UV energy source having a first peak wavelength and second UV energy source having a second peak wavelength different from the first wavelength.

Abstract: A susceptor for a processing chamber is provided including: an inner portion having a center; an outer rim disposed around the inner portion, the outer rim including a first inner side surface and a first outer side surface; and a plurality of apertures, each aperture extending from the first outer side surface to the first inner side surface. Each aperture of the plurality of apertures is located at a different angular location relative to the center of the inner portion.

Abstract: Embodiments of the present disclosure generally relate to silicon carbide coated base substrates, silicon carbide substrates thereof, and methods for forming silicon carbide coated base substrates. In some embodiments, a method includes introducing a first silicon-containing precursor to a process chamber at a first temperature of about 800° C. to less than 1,000° C. to form a first silicon carbide layer on a base substrate. The method includes introducing a second silicon-containing precursor, that is the same or different than the first silicon-containing precursor, to the process chamber at a second temperature of about 1,000° C. to about 1,400° C. to form a second silicon carbide layer on the first silicon carbide layer.

Abstract: Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.

Abstract: The present disclosure relates to gas flow substrate supports, processing chambers, and related methods and apparatus, for semiconductor manufacturing. In one or more embodiments, a substrate support applicable for semiconductor manufacturing includes a first outer surface, a ledge disposed inwardly of the first outer surface and recessed relative to the first outer surface, and a pocket defining a pocket surface that is disposed inwardly of the ledge and recessed relative to the ledge. The substrate support includes a plurality of first flow openings extending into the pocket surface, a plurality of second flow openings extending into the ledge, and a plurality of third flow openings extending into the first outer surface.

Abstract: Semiconductor devices, such as gate-all-around (GAA) devices, and methods of forming semiconductor devices are described. Selective oxidation processes that are useful in front-end of line (FEOL) and back-end of line (BEOL) applications and processes are also described. In FEOL processes, for example, selective oxidation protects silicon germanium (SiGe) layers during etching silicon (Si) channel recess when there is no dielectric inner spacer present. In BEOL processes, for example, selective oxidation protects growth of silicon germanium (SiGe) layers on the sidewall of a superlattice structure during bottom-up epitaxial growth.

Abstract: A susceptor for processing a substrate is provided including a base and a coating formed over the base. The base includes an outer rim having an inner edge, an outer edge, and a top connecting the inner edge to the outer edge; and an inner dish disposed inside the outer rim and coupled to the outer rim, the inner dish recessed from the top of the outer rim, the inner dish having a front side and an opposing back side. The coating has an outer surface that includes a first portion formed over the front side of the inner dish. The first portion of the outer surface of the coating includes a first region and a second region, the first region has a first average level of roughness, the second region has a second average level of roughness.

Abstract: The present disclosure relates to chambers, methods, apparatus, and related components for treating substrates. In one or more implementations, atomic radicals are generated using ultraviolet light, and the atomic radicals are used to treat a substrate. In one implementation, a chamber applicable for use in semiconductor manufacturing includes an internal volume defined at least partially by one or more sidewalls, one or more substrate supports disposed in the internal volume, one or more transfer openings, a gas line fluidly connecting to the internal volume from outside of the internal volume, and an ultraviolet (UV) unit. The UV unit includes one or more UV light sources configured to generate UV light having a wavelength that is within a range of 170 nm to 254 nm.

Abstract: Gate-all-around transistor devices and methods for manufacturing the same are provided. The semiconductor device includes a substrate. The substrate includes a plurality of isolation regions formed in the substrate, the plurality of isolation regions comprising an isolation material. The substrate further includes a buffer region formed in the substrate, the buffer region separating adjacent isolation regions. The semiconductor device further includes a plurality of fins, each fin formed on a corresponding isolation region of the plurality of isolation regions. Each fin includes a buffer layer contacting the isolation material and a plurality of silicon layers and a plurality of silicon germanium layers alternatingly arranged in a plurality of stacked pairs on the buffer layer.

Abstract: Method of forming a semiconductor device are provided. In some implementations, the method includes positioning a substrate into a processing chamber, the substrate having an exposed non-crystalline surface and an exposed crystalline surface. The method further includes heating the processing chamber to a temperature for deposition. The method further includes injecting a pre-treatment gas into the processing chamber. The pre-treatment gas comprises a molecule that acts to lower interfacial energy between the exposed non-crystalline surface and the exposed crystalline surface. The method further includes injecting a deposition gas into the processing chamber to selectively grow an n-type doped epitaxial silicon layer on the exposed crystalline surface.

Abstract: A processing system includes one or more processing chambers, and a system controller configured to cause the processing system to perform (a) a pre-clean process on exposed surfaces of a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surfaces of the semiconductor structure, (c) a recrystallization anneal process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer within the trench, (d) an etch process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process, to epitaxially form a source/drain region over the silicon-containing crystalline layer wi

Abstract: Embodiments of the present disclosure generally relate to silicon carbide coated base substrates, silicon carbide substrates thereof, and methods for forming silicon carbide coated base substrates. In some embodiments, a method includes introducing a first silicon-containing precursor to a process chamber at a first temperature of about 800° C. to less than 1,000° C. to form a first silicon carbide layer on a base substrate. The method includes introducing a second silicon-containing precursor, that is the same or different than the first silicon-containing precursor, to the process chamber at a second temperature of about 1,000° C. to about 1,400° C. to form a second silicon carbide layer on the first silicon carbide layer.

Abstract: A susceptor including a generally circular body having a face with a radially inward section and a radially outward section proximate a circumference of the body, the radially outward section having at least one ring extending upward for contacting a bottom surface of a substrate, and wherein the radially inward section lacks a ring extending upward from the face.

Abstract: A contactless tire inspection apparatus for tire tread depth measurement using 3D reconstruction includes a driver side (DS) measurement device (MD) and a passenger side (PS) MD. The DS MD includes a DS light source configured to, responsive to receiving a trigger signal (TS), project a first structured illumination (SI) onto a DS tire of a vehicle and at least one DS camera configured to, responsive to receiving the TS, capture DS image(s) of the first SI projected onto the DS tire for 3D reconstruction. The PS MD includes a PS light source configured to, responsive to receiving the TS, project a second SI onto a PS tire of the vehicle and at least one PS camera configured to, responsive to receiving the TS, capture PS image(s) of the second SI projected onto the PS tire for 3D reconstruction when the at least one DS camera captures DS image(s).