Abstract: A memory cell includes a bottom electrode, a thermal preservation layer, a first dielectric layer, a variable resistance layer, and a top electrode. The bottom electrode includes a first electrode and a second electrode spatially separated from the first electrode. The thermal preservation layer is partially sandwiched between the first electrode and the second electrode. The first dielectric layer laterally surrounds the bottom electrode and the thermal preservation layer. The variable resistance layer is disposed on the second electrode, the thermal preservation layer, and the first dielectric layer. The top electrode is disposed on the variable resistance layer.

Abstract: An electronic device includes: a substrate; a gate electrode disposed on the substrate; a data line disposed on the substrate and extending along an extension direction; a power supply circuit disposed on the substrate; and a connecting member disposed on the substrate and electrically connected to the gate electrode, wherein the connecting member includes a first part overlapped with the gate electrode and a second part not overlapped with the gate electrode, wherein in a top view, an outline of the connecting member includes a first curve segment, wherein a maximum width of the data line in a direction perpendicular to the extension direction is less than a maximum width of the power supply circuit in the direction.

Abstract: A centrifugal compressor and a method of operating a centrifugal compressor. The centrifugal compressor includes: an impeller configured to suction a gas to be compressed; a diffuser disposed downstream of the impeller to pressurize the gas, the diffuser comprising a movable ring, a main passage in which the gas flows past the ring, and an openable branch passage; and a circulation loop comprising an inlet and an outlet, the outlet being in communication with an inlet of the impeller; the branch passage is disposed to be in communication with the main passage and the circulation loop when the ring moves into the main passage so that a portion of the gas in the main passage passes through the circulation loop and returns to the impeller so as to be suctioned, and to be closed when the ring is withdrawn from the main passage.

Abstract: A radio frequency (RF) device and a voltage generation and harmonic suppressor thereof are provided. The RF device includes the voltage generation and harmonic suppressor and a RF circuit. The voltage generation and harmonic suppressor is configured to receive a RF signal to output at least one direct current (DC) voltage related to the RF signal, and configured to suppress a harmonic generated by the RF signal in the voltage generation and harmonic suppressor. The RF circuit is configured to receive the RF signal, and configured to perform an operation according to the at least one DC voltage.

Abstract: A quick release buckle includes a first connecting member, a second connecting member, and a locking member, where the first connecting member is provided with a first chamber, and the second connecting member is provided with a second chamber; the locking member is provided with a first locking part and a second locking part connected to each other; the first locking part is located inside the first chamber, and is connected to the first connecting member through a reset mechanism; and the second locking part is detachably connected to the second chamber.

Abstract: In various embodiments, an improved structure for a PCM device is provided. The improved structure is configured to help prevent heat dissipation. In one example, the PCM device is an PCM RF Switch, which has a substrate, a heater, a dielectric/insulator layer, oxidation layers, electrodes, a PCM region, and/or any other components. The oxidation layers are configured to help prevent heat dissipation from the heater.

Abstract: A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value. A memory device is also disclosed herein.

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a first fin, and the first fin has a channel region and a source/drain region. The method includes forming a stack structure over the first fin, and the stack structure includes a first semiconductor layer and a second semiconductor layer vertically stacked over the fin. The method also includes removing a portion of the second semiconductor layer in the channel region, and a portion of the first semiconductor layer is remaining in the channel region. The method further includes forming a cladding layer over the remaining first semiconductor material layer in the channel region to form a nanostructure, wherein the nanostructure has a dumbbell shape. The method includes forming a gate structure surrounding the nanostructure.

Abstract: A method and apparatus for sending a debugging instruction, an electronic device and a computer readable storage medium are provided. The method may include: after acquiring a debugging instruction sent by an operating terminal, determining a debugged terminal and a first edge communication node corresponding to the debugged terminal according to the debugging instruction, and determining a debugging communication link between the first edge communication node and the debugged terminal, the first edge communication node being determined based on first edge communication node information sent by the debugged terminal, and the first edge communication node information being determined and obtained based on an edge node computing application locally installed on the debugged terminal, and sending an debugging operation included in the debugging instruction to the debugged terminal through the debugging communication link.

Abstract: A display detection device includes a panel, a detection board, and a detection adapter board. The panel is configured to display. The detection board is coupled to the panel, and is configured to input a detection signal. The detection adapter board is coupled to the panel, and is configured to respond to the detection signal to generate a detection result.

Abstract: A selector structure may include a bottom electrode including a bottom low thermal conductivity (LTC) metal and a first bottom high thermal conductivity (HTC) metal, a first switching film on the bottom electrode and having an electrical resistivity switchable by an electric field, and a first top electrode on the first switching film and including a first top low thermal conductivity (LTC) metal and a first top high thermal conductivity (HTC) metal.

Abstract: A method of forming a semiconductor device includes forming an opening in a dielectric layer, and forming a barrier layer in the opening. A combined liner layer is formed over the barrier layer by first forming a first liner layer over the barrier layer, and forming a second liner layer over the first liner layer, such that the first liner layer and the second liner layer intermix. A conductive material layer is formed over the combined liner layer, and a thermal process is performed to reflow the conductive material layer.

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

Abstract: A semiconductor device includes a fin extending from a substrate. The fin has a source/drain region and a channel region. The channel region includes a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer and vertically separated from the first semiconductor layer by a spacing area. A high-k dielectric layer at least partially wraps around the first semiconductor layer and the second semiconductor layer. A metal layer is formed along opposing sidewalls of the high-k dielectric layer. The metal layer includes a first material. The spacing area is free of the first material.

Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

Abstract: A data storage method and system, applied in a network system of distributed ledger technology. The method comprises: storing, by a first node, data of information units of the network system; determining, by a second node, a designated origin signal including an identifier of at least one origin information unit; obtaining, by the second node, data of the information units of the network system from the first node; determining, by the second node, a designated destination signal including an identifier of a destination information unit; determining, by the second node, a shortest path data from the origin information unit to the destination information unit according to the designated origin signal, the data of the information units of the network system, and the designated destination signal; and storing, by the second node, data of all information units included in the shortest path data.

Abstract: A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.