Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.

Abstract: Provided are ferroelectric tunnel junction (FTJ) structures, memory devices, and methods for fabricating such structures and devices. An FTJ structure includes a first electrode, a ferroelectric material layer, and a catalytic metal layer in contact with the ferroelectric material layer.

Abstract: A fluoride-based resin prepreg and a circuit substrate using the same are provided. The fluoride-based resin prepreg includes 100 PHR of a fluoride-based resin and 20 to 110 PHR of an inorganic filler. Based on a total weight of the fluoride-based resin, the fluoride-based resin includes 10 to 80 wt % of polytetrafluoroethylene (PTFE), 10 to 50 wt % of fluorinated ethylene propylene (FEP), and 0.1 to 40 wt % of perfluoroalkoxy alkane (PFA). The circuit substrate includes a fluoride-based resin substrate and a circuit layer that is formed on the fluoride-based resin substrate.

Abstract: In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

Abstract: A voltage state detector includes a voltage drop circuit, a pull-down circuit, a load circuit, a transistor, a pull-up circuit, first and second output terminals, and a logic circuit. The pull-down circuit is coupled to the voltage drop circuit. The transistor has a first terminal coupled to the load circuit, a second terminal coupled to the pull-down circuit, and a control terminal coupled to the voltage drop circuit. The pull-up circuit is coupled to the load circuit and the voltage drop circuit. The first output terminal is coupled to the first terminal of the transistor for outputting a first state determination signal. The second output terminal is coupled to the voltage drop circuit for outputting a second state determination signal. The logic circuit includes a NOR gate for performing an NOR operation on the first state determination signal and the second state determination signal to output a control signal.

Abstract: A semiconductor structure includes an inductive metal line located in a dielectric material layer that overlies a semiconductor substrate and laterally encloses a first area; and an array of first ferromagnetic plates including a first ferromagnetic material and overlying or underlying the inductive metal line. For any first point that is selected within volumes of the first ferromagnetic plates, a respective second point exists within a horizontal surface of the inductive metal line such that a line connecting the first point and the second point is vertical or has a respective first taper angle that is less than 20 degrees with respective to a vertical direction. The magnetic field passing through the first ferromagnetic plates is applied generally along a hard direction of magnetization and the hysteresis effect is minimized.

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.

Abstract: An interlayer connective structure is suitable for being formed in a wiring board, in which the wiring board includes two traces and an insulation part between the traces. The insulation part has a through hole. The interlayer connective structure located in the through hole is connected to the traces. The interlayer connective structure includes a column and a pair of protuberant parts. The protuberant parts are located at two ends of the through hole respectively and connected to the column and the traces. The protuberant parts stick out from the outer surfaces of the traces respectively. Each of the protuberant parts has a convex curved surface, in which the distance between the convex curved surface and the axis of the through hole is less than the radius of the through hole.

Abstract: A prepreg and a metallic clad laminate are provided. The prepreg includes a reinforcing material and a thermosetting resin layer. The thermosetting resin layer is formed by immersing the reinforcing material in a thermosetting resin composition. The thermosetting resin composition includes a polyphenylene ether resin, a liquid polybutadiene resin, a crosslinker, and fillers. Based on a total weight of the thermosetting resin composition being 100 phr, an amount of the fillers ranges from 50 phr to 70 phr. The fillers include a granular dielectric filler and a flaky thermal conductive filler. The metallic clad laminate is formed by disposing at least one metal layer onto the prepreg.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: A memory device includes a transistor device; a memory cell electrically coupled to a source or drain of the transistor device, wherein the memory cell includes an FJT structure; and a heating structure formed around the memory cell on a plurality of sides. The FJT structure includes a first conductive electrode having sidewalls that extend in a vertical direction to a first elevation level, a second conductive electrode having sidewalls that extend in the vertical direction to the first elevation level, and a switching barrier disposed between the first conductive electrode and the second conductive electrode and having sidewalls that extend in the vertical direction to the first elevation level, wherein the vertically extending sidewalls of the first conductive electrode, the second conductive electrode, and the switching barrier terminate at the first elevation level. The switching barrier includes ferroelectric (Fe) material that may be polarized to store information.

Abstract: A refrigerator includes a refrigerator body, an ice maker, a refrigeration cycle system, and a controller. The refrigerator body includes a chamber. The ice maker is located in the chamber and is configured to make ice. The ice maker includes two refrigerant pipes. The refrigeration cycle system includes a compressor, a condenser, and two cooling flow paths. The two cooling flow paths are connected to the two refrigerant pipes, respectively, and the two cooling flow paths are configured to cool the ice maker. The controller is configured to control the compressor to be turned on or off and control the two cooling flow paths to open or be closed, so as to cool the ice maker through at least one of the two refrigerant pipes.

Abstract: An anti-biofouling shape-memory composite aerogel includes a unidirectional chitosan aerogel channel, a plant polyphenol coating, and a polyphenol/iron ion chelate. The plant polyphenol coating is evenly distributed on an inner wall of the unidirectional chitosan aerogel channel, and the polyphenol/iron ion chelate is located at a top end of the unidirectional chitosan aerogel channel. The anti-biofouling chitosan-based composite aerogel has an evaporation rate of 1.96 kg·m?2·h?1 at an illumination intensity of 1 kW/m2. The composite aerogel has shape-memory properties, and can quickly restore its original shape in water after extrusion, thereby accelerating the diffusion of substances to complete the modification of inner channels. In this way, desirable anti-biofouling ability is achieved, and excellent structural stability as well as continuous and efficient photothermal water evaporation are guaranteed in a complex water environment.

Abstract: A memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.

Abstract: A memory device, a semiconductor device and a manufacturing method of the memory device are provided. The memory device includes first, second and third stacking structures, first and second channel structures, a gate dielectric layer, a switching layer, and first and second gate structures. The first, second and third stacking structures are laterally spaced apart from one another, and respectively comprise a conductive layer, an isolation layer and a channel layer. The third stacking structure is located between the first and second stacking structures. The first channel structure extends between the channel layers in the first and third stacking structures. The second channel structure extends between the channel layers in the second and third stacking structures. The gate dielectric layer and the first gate structure wrap around the first channel structure. The switching layer and the second gate structure wrap around the second channel structure.

Abstract: A mask inspection apparatus includes a booth, a carrier, two linear scanners, a light source module and a control unit. The booth includes a platform including a slot. The carrier is movable along the slot. The carrier includes a support face for supporting the mask, guiding elements on the support face, and an inspection window in the support face. The support face extends above the platform. The linear image scanners are vertically movable respectively blow and above the platform. The light source module includes two light boxes on the platform. The light boxes are operable to cast light on an upper face of the mask in an upper position. The light boxes are operable to cast light on a lower face of the mask in a lower position. The control unit is electrically connected to the carrier, the linear image scanner and the light source module.

Abstract: A mask inspection machine includes a platform unit for carrying a transparent container. The transparent container includes a lower window and an upper window. The platform unit includes a platform and a carrier. The platform includes a slot. The carrier is movable on the platform along the slot. The carrier includes a plate and guiding elements. The plate includes a support face including an inspection window corresponding to the lower window of the transparent container. The guiding elements are connected to the support face for guiding the transparent container onto the support face.

Abstract: A loop filter, and a timing recovery method and apparatus are provided. The loop filter includes: N input terminals configured to receive N first signals; where N is any integer greater than or equal to 2; a source filter, including: an integral signal terminal and an addition terminal; a first gain processing module configured to perform first gain processing on the N first signals to obtain a second signal, and output the second signal to the addition terminal; a second gain processing module configured to perform second gain processing on the N first signals to obtain a third signal, and output the third signal to the integral signal terminal; and a source filter configured to integrate the third signal received by the integral signal terminal to obtain a fourth signal, and obtain a fifth signal according to the fourth signal and the second signal received by the addition terminal.

Abstract: A manufacturing method for circuit board structure includes steps of providing a carrier, forming a first build-up layer including a plurality of first circuits, forming a second build-up layer including a plurality of second circuits on a side of the first build-up layer located away from the carrier, attaching a side of the second build-up layer located away from the first build-up layer to a core layer, and removing the carrier from the first build-up layer, where the first circuits are finer than the second circuits.