Abstract: A polyethylene glycol-drug conjugate and a use thereof, specifically relating to a polyethylene glycol-drug conjugate as shown in formula A, a stereoisomer thereof or a pharmaceutically acceptable salt thereof; an intermediate for the preparation of the polyethylene glycol-drug conjugate, the stereoisomer thereof or the pharmaceutically acceptable salt thereof; a pharmaceutical composition containing the polyethylene glycol-drug conjugate, the stereoisomer thereof or the pharmaceutically acceptable salt thereof; and a use of the polyethylene glycol-drug conjugate, the stereoisomer thereof or the pharmaceutically acceptable salt thereof in the preparation of a drug.

Abstract: Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells including a first string of memory cells and a second string of memory cells; and a first switch including: a first electrode connected to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells, and a second electrode connected to a first global bit line, wherein gate electrodes of the first string of memory cells are connected to a first word line and gate electrodes of the second string of memory cells are connected to a second word line.

Abstract: A display apparatus includes a driving backplane, a plurality of light emitting devices, a first encapsulation pattern, and a second encapsulation pattern. The light emitting devices are disposed on the driving backplane and electrically connected to the driving backplane. The first encapsulation pattern includes a first portion and a second portion. The first portion is disposed on the driving backplane. The second portion is disposed on the first portion of the first encapsulation pattern, covers a plurality of sidewalls of the light emitting devices, and has a plurality of first openings overlapping a plurality of top surfaces of the light emitting devices. The second encapsulation pattern is disposed on the first portion of the first encapsulation pattern and has a plurality of second openings. The second openings are overlapped with the top surfaces of the light emitting devices and the second portion of the first encapsulation pattern.

Abstract: A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure.

Abstract: An image processing circuit performs super-resolution (SR) operations. The image processing circuit includes memory to store multiple parameter sets of multiple artificial intelligence (AI) models. The image processing circuit further includes an image guidance module, a parameter decision module, and an SR engine. The image guidance module operates to detect a representative feature in an image sequence including a current frame and past frames within a time window. The parameter decision module operates to adjust parameters of one or more AI models based on a measurement of the representative feature. The SR engine operates to process the current frame using the one or more AI models with the adjusted parameters to thereby generate a high-resolution image for display.

Abstract: A folding seat support frame includes an upper support frame detachably connected to a seat fabric and a lower support frame connected to the upper support frame, where the upper support frame includes an upper connector, short rods rotationally connected to the upper connector at a first limited angle, and upper connecting rods rotationally connected to the short rods at a second limited angle; the lower support frame includes a lower connector and lower connecting rods rotationally connected to the lower connector at a third limited angle; the lower connector and the upper connector are coaxially and rotationally connected; when the folding seat support frame is in an unfolded state, the lower connecting rods and the short rods are oriented to a side of the lower connector; when the folding seat support frame is in a folded state, the short rods are butted against the lower connector.

Abstract: A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

Abstract: A switch device includes a first radio-frequency (RF) terminal, a second RF terminal, a first transistor, a second transistor, and a variable resistance element. The first transistor includes a first terminal coupled to the first RF terminal, a second terminal, and a control terminal coupled to a control signal terminal providing a control signal. The second transistor includes a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the second RF terminal, and a control terminal. The variable resistance element is coupled between the second terminal of the first transistor and a bias voltage terminal. When the first transistor and the second transistor are in a transient state, the variable resistance element provides a lower resistance. When the first transistor and the second transistor are in an ON state, the variable resistance element provides a higher resistance.

Abstract: Methods and systems for uniformly cooling a dome within a plasma treatment system are disclosed. The methods and systems utilize a diffuser including a perforated plate and a cone. The perforated plate includes a center portion and multiple arrays of holes with each array being located circumferentially at a different distance from the center. The cone extends away from the center. The diffuser spreads cooling gas more uniformly across the surface of the dome.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

Abstract: A method for manufacturing a resistive random access memory structure is provided. The method includes providing a substrate, and the substrate includes an array region and a peripheral region. The method includes forming a first low-k dielectric layer in the peripheral region, and the first low-k dielectric layer has a dielectric constant of less than 3. The method includes forming a plurality of memory cells on the substrate and in the array region. The method includes forming a dummy memory cell at a boundary between the array region and the peripheral region. The method includes forming a gap-filling dielectric layer on the substrate. The method includes forming a plurality of first conductive plugs in the gap-filling dielectric layer, and each of the plurality of first conductive plugs is in contact with one of the plurality of memory cells.

Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

Abstract: The present invention relates to a cyber security method, which includes: in a first device: randomly generating an ephemeral decryption key (EDK) in response to an input of an authentication information (AI); transmitting the EDK to a third device and retrieving a token index (TI) from the third device; encrypting an ID info to generate an electronic digital signature (EDS) based on a part of the EDK to generate an authentication token (AT) accordingly; and combining the AI, the ID info, the TI and the AT to form an ephemeral string and sending the ephemeral string to a second device; and in the second device: acquiring the AI, the ID info, the TI and the AT by parsing the ephemeral string and requesting to retrieve the EDK from the third device based on the TI; and decrypting the AT and verifying the EDS based on the EDK.

Abstract: A semiconductor pattern is provided in the present invention, including a first line extending to one end in a first direction and a second line extending in a second direction perpendicular to the first direction and adjacent to the end of the first line in the first direction, wherein the end of the first line is provided with a rounding feature, the first line has a width in the second direction, and the width is gradually increased to a maximum width toward the end and gradually converged to form the rounding feature.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: A circuit board includes a first external circuit layer, a first substrate, a second substrate, a third substrate, and a conductive through hole structure. The first substrate includes conductive pillars electrically connecting the first external circuit layer and the second substrate. The second substrate has an opening and includes a first dielectric layer. The opening penetrates the second substrate, and the first dielectric layer fills the opening. The third substrate includes an insulating layer, a second external circuit layer, and conductive holes. A conductive material layer of the conductive through hole structure covers an inner wall of a through hole and electrically connects the first and the second external circuit layers to define a signal path. The first external circuit layer, the conductive pillars, the second substrate, the conductive holes and the second external circuit layer are electrically connected to define a ground path surrounding the signal path.

Abstract: The invention discloses a digital signature system. The digital signature system comprises an electronic device and a data storage device. The electronic device generates a specific data by executing a specific operation, and performs a calculation operation on the specific data via a hash algorithm to generate a hash data. The data storage device comprises a controller, a plurality of flash memories, and a data transmission interface. The electronic device transmits the hash data to the data storage device via the transmission interface. The controller comprises a firmware. The firmware reads an unclonable function, and generates a private key according to the unclonable function, and encrypts the hash data by the private key to obtain a digital signature. The data storage device transmits the digital signature to the electronic device via the transmission interface.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a plurality of memory stacks disposed over a substrate and respectively having a plurality of conductive segments stacked onto one another. One or more data storage structures are on the plurality of memory stacks, one or more selectors are over the one or more data storage structures, and an upper conductor over the one or more selectors. The plurality of memory stacks include a first memory stack, a second memory stack, and a third memory stack. The first memory stack and the third memory stack are closest memory stacks to opposing sides of the second memory stack. The first memory stack is closer to the second memory stack than the third memory stack.

Abstract: There is provided a phase shifter having a phase shift region and a peripheral region, and including a first substrate, a second substrate and a dielectric layer between such two substrates; the first substrate includes a first dielectric substrate, a first electrode and a first auxiliary structure; the second substrate includes a second dielectric substrate, a second electrode and a second auxiliary structure; the phase shift region includes overlapping regions; the first electrode and the second electrode are located in the phase shift region, and have orthographic projections, on the first dielectric substrate, overlapped at least partially in the overlapping regions; the first auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the first dielectric substrate; the second auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the second dielectric substrate.