Patents by Inventor Sheng Lu

Sheng Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250111123
    Abstract: A method for checking standard cell spacing in a design includes providing a first standard cell. A cell environment of the first standard cell is determined and a first feasible distance between a first boundary of the standard cell and a boundary of a first adjacent cell based on the cell environment is determined. A second feasible distance between a second boundary of the standard cell and a boundary of a second adjacent cell based on the cell environment is determined. A feasible spacing between the first standard cell and a second standard cell is provided, and the feasible spacing is evaluated based on the first feasible distance, the second feasible distance and a cell pitch of the first standard cell. An integrated circuit is fabricated that includes the first standard cell in response on the evaluating.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Hung-Chih Ou, Yu-Sheng Lu, Wen-Hao Chen
  • Publication number: 20250089578
    Abstract: A magnetic tunnel junction (MTJ) structure and a memory cell are provided. The MTJ includes a barrier layer, a free layer and a metal oxide cap layer. The free layer is disposed on the barrier layer. The metal oxide cap layer is disposed on the free layer. The metal oxide cap layer has a first surface and a second surface opposite to the first surface. The first surface of the metal oxide cap layer is in contact with the free layer. In a direction of a thickness of the metal oxide cap layer, both of an oxygen concentration at the first surface of the metal oxide cap layer and an oxygen concentration at the second surface of the metal oxide cap layer are higher than an oxygen concentration in a middle portion of the metal oxide cap layer.
    Type: Application
    Filed: September 13, 2023
    Publication date: March 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zhi-Ren Xiao, Nuo Xu, Po-Sheng Lu, Yuan-Hao Chang, Zhiqiang Wu, Yu-Jen WANG
  • Patent number: 12236313
    Abstract: A method is provided for remotely assuring the quality and transportation of offsite construction components. The method involves placing a code on the module, where the code contains identity information about the module. Then the code is scanned to obtain the identity information and to upload it to a blockchain data storage facility. Access is allowed to the identity information in the blockchain data storage facility to relevant parties for the purpose of remotely inspecting the module to verify its quality. Based on this verification the module may be delivered to a transportation facility for transport. During transport location information about the module is collected and uploading it to blockchain data storage facility. Second access is allowed to the location information stored in the blockchain data storage facility to allow relevant parties to remotely understand the transportation situation of the module.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: February 25, 2025
    Assignee: THE UNIVERSITY OF HONG KONG
    Inventors: Wilson Wei Sheng Lu, Anthony Garon Yeh, Fan Xue, Liupengfei Wu
  • Patent number: 12216407
    Abstract: A multi-spray RRC process with dynamic control to improve final yield and further reduce resist cost is disclosed. In one embodiment, a method, includes: dispensing a first layer of solvent on a semiconductor substrate while spinning at a first speed for a first time period; dispensing the solvent on the semiconductor substrate while spinning at a second speed for a second time period so as to transform the first layer to a second layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a third speed for a third time period so as to transform the second layer to a third layer of the solvent; dispensing the solvent on the semiconductor substrate while spinning at a fourth speed for a fourth time period so as to transform the third layer to a fourth layer of the solvent; and dispensing a first layer of photoresist on the fourth layer of the solvent while spinning at a fifth speed for a fifth period of time.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hsuan Chuang, Po-Sheng Lu, Shou-Wen Kuo, Cheng-Yi Huang, Chia-Hung Chu
  • Patent number: 12190033
    Abstract: A method for a parallelism-aware wavelength-routed optical networks-on-chip design is proposed, which is executed by a computer, the method comprising using the computer to perform the following: providing a WRONoC netlist, design specs and design rules; performing a network construction such that potential positions of each core of a plurality of cores, a plurality of waveguides and a plurality of microring resonators (MRRs) are determined to create a topology; performing a message routing to minimize MRR type usage of the MRRs in the topology; and performing a MRR radius selection to select a radius from MRR-radius options for each MRR type in said topology based on a simulated annealing.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: January 7, 2025
    Assignee: ANAGLOBE TECHNOLOGY, INC.
    Inventors: Kuan-Cheng Chen, Yan-Lin Chen, Yu-Sheng Lu, Yao-Wen Chang, Yu-Tsang Hsieh
  • Patent number: 12174779
    Abstract: An FPGA-based USB3.0/3.1 control system, including: a USB control module including a USB3.0 control module and/or a USB3.1 control module; a PCS logic module connected to the USB control module via a PIPE interface; an FPGA Serdes serial communication module connected to the PCS logic module; and an external daughter card module connected to the FPGA Serdes serial communication module, wherein the PCS logic module, the FPGA Serdes serial communication module and the external daughter card module are connected in sequence to achieve a port physical layer function for testing the USB 3.0 control module and the USB 3.1 control module. The control system solves the cumbersome problems of incomplete emulation verification, test mode limitations, and unchangeable hardware functions in the prior art.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 24, 2024
    Assignee: Corigine (Shanghai), Inc.
    Inventors: Zhihao Yin, Sheng Lu, Kai Fan, Xiao Xiao, Kai Cheng
  • Publication number: 20240411102
    Abstract: An optical driving apparatus, including: a fixed member; a driven member that is movable with respect to the fixed member; and a guiding member that restricts the driven member from moving in a predetermined direction with respect to the fixed member, wherein the guiding member has: a first groove in a V-shaped cross-sectional shape, which is formed on any one of the fixed member or the driven member; a first convex portion fitting into the first groove, which is formed on another of the fixed member or the driven member; and a plurality of microspheres interposed in a gap between the first groove and the first convex portion and disposed in a longitudinal direction of the first groove and in a direction perpendicular to the longitudinal direction to generate rolling friction.
    Type: Application
    Filed: August 20, 2024
    Publication date: December 12, 2024
    Inventors: Yasushi TAKAHASHI, Minoru KUWANA, Yasuhiro OKAMOTO, Takao KOBAYASHI, Takehiro KANO, Sheng LU
  • Publication number: 20240395734
    Abstract: An electronic device includes a printed circuit board, a semiconductor chip, and a shielding unit. The semiconductor chip is mounted and electrically connected to the printed circuit board, and includes a magnetic memory element. The shielding unit includes a magnetic material, and is mounted to the printed circuit board to at least partially cover the magnetic memory element so as to reduce interference from an external magnetic field on the magnetic memory element.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Wei CHIANG, Po-Sheng LU, Yuan-Jen LEE, Nuo XU
  • Publication number: 20240389466
    Abstract: A semiconductor device includes a bottom electrode and a magnetic tunneling junction (MTJ) element over the bottom electrode. The MTJ element includes a top magnetic plate, a bottom magnetic plate, and a barrier layer between the top magnetic plate and the bottom magnetic plate. An edge portion of the bottom magnetic plate extends beyond sidewalls of the top magnetic plate. The semiconductor device also includes a spacer disposed on the sidewalls of the top magnetic plate but not on sidewalls of the bottom magnetic plate, and a top electrode over the top magnetic plate.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Chih-Fan Huang, Po-Sheng Lu, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
  • Publication number: 20240381783
    Abstract: An MRAM cell block and a magnetic shielding structure for the MRAM cell block are incorporated into a metal interconnect of an integrated circuit (IC) device. The magnetic shielding structure may be provided by metallization layers and via layers having wires and vias that incorporate a magnetic shielding material. The magnetic shielding material may form the wires and vias, form a liner around the wires, or may be a layer of the wires. The wires and vias may also include a metal that is more conductive than the magnetic shielding material. The metal interconnect may include layers above or below the magnetic shielding structure that lack the magnetic shielding material and are more conductive. The MRAM cell block with the magnetic shielding structure is optionally provided as a standalone memory device or incorporated into a 3-D IC device that includes a second substrate having a conventional metal interconnect.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 14, 2024
    Inventors: Nuo Xu, Yuan Hao Chang, Po-Sheng Lu, Zhiqiang Wu
  • Publication number: 20240371786
    Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.
    Type: Application
    Filed: July 14, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nuo Xu, Yuan-Hao Chang, Po-Sheng Lu, Zhiqiang Wu
  • Publication number: 20240348912
    Abstract: Embodiments described in the present application provide a video processing method, device, computer equipment, and storage medium, displaying a video picture of a panoramic video through a user interface, and, in response to a selection operation on the video picture, determining a target object to be photographed in the panoramic video, then, acquiring a target shooting field of view of the target object in the video picture, and in response to the video shooting instruction, performing video recording on the target object based on the target shooting field of view to generate a target planar video. The embodiment of the present application can simplify the steps of obtaining the target planar video from the panoramic video and improve the efficiency of acquiring a target planar video from a panoramic video.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Applicant: Arashi Vision Inc.
    Inventors: Sheng LU, Jun ZHENG
  • Publication number: 20240344783
    Abstract: A cooling structure having a metal plating layer is provided with a substrate, a first metal plating layer and a second metal plating layer that are made of materials different from each other and formed on the substrate by different processes. The first metal plating layer is formed on the substrate by a wetting process. The second metal plating layer having a thickness ranging from 0.1 ?m to 5 ?m is formed on the first metal plating layer by a sputtering process. The second metal plating layer includes at least three blocks arranged at intervals, and at least two adjacent ones of the at least three blocks have a distance therebetween that is not equal to a distance between another two adjacent ones of the at least three blocks.
    Type: Application
    Filed: April 13, 2023
    Publication date: October 17, 2024
    Inventors: CHING-MING YANG, KUN-LIN CHIH, YI-SHENG LU, TZE-YANG YEH
  • Patent number: 12110337
    Abstract: This disclosure provides isolated antibodies that bind specifically to CD27 with high affinity. The disclosure provides methods for treating a subject afflicted with a cancer comprising administering to the subject a therapeutically effective amount of an anti-CD27 antibody as monotherapy or in combination with a checkpoint inhibitor, such as an anti-PD-1, anti-PD-L1, or anti-CTLA-4 antibody.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: October 8, 2024
    Assignee: Bristol-Myers Squibb Company
    Inventors: Li-Sheng Lu, Mark J. Selby, Alan J. Korman, Shrikant Deshpande, Mohan Srinivasan, Jun Zhang, Haichun Huang, Guodong Chen, Richard Y. Huang, Ekaterina Deyanova
  • Patent number: 12107054
    Abstract: A semiconductor package, a semiconductor device and a shielding housing for a semiconductor package are provided. The semiconductor package includes a semiconductor chip having a first region and a second region beside the first region; and a shielding housing encasing the semiconductor chip, made of a magnetic permeable material, and including a first shielding plate, a second shielding plate opposite to the first shielding plate and a shielding wall extending between the first shielding plate and the second shielding plate. The first shielding plate has an opening exposing the first region and includes a raised portion surrounding the opening and a flat portion beside the raised portion and shielding the second region. A first distance from a level of the semiconductor chip to an outer surface of the raised portion is greater than a second distance from the level to an outer surface of the flat portion.
    Type: Grant
    Filed: February 23, 2023
    Date of Patent: October 1, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nuo Xu, Yuan-Hao Chang, Po-Sheng Lu, Zhiqiang Wu
  • Publication number: 20240324245
    Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.
    Type: Application
    Filed: June 3, 2024
    Publication date: September 26, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Shih-Hao LIN, Po-Sheng LU, Chenchen Jacob WANG, Yuan Hao CHANG, Ping-Wei WANG
  • Publication number: 20240312758
    Abstract: Apparatuses, systems, and methods for adjusting beam current using a feedback loop are provided. In some embodiments, a system may include a first anode aperture configured to measure a current of an emitted beam during inspection of a sample, wherein the first anode aperture is positioned in an environment that is configured to support a vacuum pressure of less than 3×10?10 torr and a controller including circuitry configured to cause the system to perform: generating a feedback signal when a difference between the measured current and a setpoint current exceeds a threshold value and adjusting a voltage of an extractor voltage supply based on the feedback signal during inspection of the sample such that a difference between an adjusted current of the emitted beam and the setpoint current is below the threshold value.
    Type: Application
    Filed: May 30, 2022
    Publication date: September 19, 2024
    Inventors: Zheng FAN, Bruno LA FONTAINE, He Sheng LU, Gao Xing YIN, Shun ZHANG, Zhenfeng ZHAO
  • Publication number: 20240281629
    Abstract: A method is provided for remotely assuring the quality and transportation of offsite construction components. The method involves placing a code on the module, where the code contains identity information about the module. Then the code is scanned to obtain the identity information and to upload it to a blockchain data storage facility. Access is allowed to the identity information in the blockchain data storage facility to relevant parties for the purpose of remotely inspecting the module to verify its quality. Based on this verification the module may be delivered to a transportation facility for transport. During transport location information about the module is collected and uploading it to blockchain data storage facility. Second access is allowed to the location information stored in the blockchain data storage facility to allow relevant parties to remotely understand the transportation situation of the module.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Applicant: THE UNIVERSITY OF HONG KONG
    Inventors: Wilson Wei Sheng LU, Anthony Garon YEH, Fan XUE, Liupengfei WU
  • Publication number: 20240234201
    Abstract: An isolation structure, comprising: an isolation material layer, filled in a trench of a substrate; and a protection layer, having two portions extending from a topmost surface of the substrate to a top surface of the isolation material layer across boundaries of the trench, and covering opposite edges of the isolation material layer, wherein the two portions of the protection layer are laterally spaced apart from each other, and the protection layer has an etching selectivity with respect to the isolation material layer.
    Type: Application
    Filed: March 26, 2024
    Publication date: July 11, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Ying-Fu Tung, Chun-Sheng Lu, Mu-Lin Li
  • Patent number: 12022664
    Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 25, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jui-Lin Chen, Chenchen Jacob Wang, Hsin-Wen Su, Ping-Wei Wang, Yuan-Hao Chang, Po-Sheng Lu, Shih-Hao Lin