Abstract: A method includes forming a magnetic tunnel junction (MTJ) stack over a substrate. The MTJ stack including a top magnetic layer, a barrier layer, and a bottom magnetic layer. The method also includes patterning the top magnetic layer in a first etch process, after the patterning of the top magnetic layer depositing a spacer on sidewalls of the patterned top magnetic layer, and patterning the bottom magnetic layer in a second etch process.

Abstract: An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor on a substrate. The source/drain regions of the first nanostructure are electrically isolated from the semiconductor substrate by bottom dielectric regions. The source/drain regions of the second nanostructure transistor in direct contact with the semiconductor substrate.

Abstract: A shutter includes a window frame, a plurality of blade structures, an intake driving unit and an airflow guiding unit. The window frame has an upper frame portion, a lower frame portion and two side frame portions. The blade structures are disposed on the window frame, and each has a through hole and a plurality of outlets. The intake driving unit is disposed in the upper frame portion. The airflow guiding unit is disposed in at least one of the two side frame portions. Each of the through holes of the blade structures communicates with the inside of at least one of the two side frame portions.

Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

Abstract: A method for forming a semiconductor structure includes forming a gate electrode layer over a semiconductor substrate, forming a first spacer layer to cover a sidewall of the gate electrode layer, recessing the first spacer layer to expose an upper portion of the sidewall of the gate electrode layer, forming a metal material to cover an upper surface and the upper portion of the sidewall of the gate electrode layer; reacting a semiconductor material of the gate electrode layer with the metal material using an anneal process to form a silicide layer, and removing the metal material after the anneal process.

Abstract: A method for forming an isolation structure includes: forming a trench at a surface of a substrate; forming a mask pattern on the substrate, wherein the mask pattern has an opening communicated with the trench; filling a first isolation material layer in the opening and the trench, wherein a surface of the first isolation material layer defines a first recess; filling a second isolation material layer into the first recess; partially removing the first and second isolation material layers, to form a second recess, performing first and second oblique ion implantation processes, to form damage regions in the first isolation material layer; performing a decoupled plasma treatment, to transform portions of the damage regions into a protection layer having etching selectivity with respect to the damage regions; and removing the damage regions.

Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.

Abstract: A method for displaying and detecting temperature field distribution of a fluid surface applies a stimulus-responsive compound to high-resolution and high-precision imaging of a temperature field of a fluid for the first time. Under physical or chemical stimulation, an imaging developer visualizes the temperature field distribution of the fluid surface. The method for displaying and detecting temperature field distribution of the fluid surface includes dissolving or dispersing an imaging reagent in a fluid, stimulating the fluid surface to change a color or a fluorescence of the imaging reagent, collecting images of a generated color or a generated fluorescence to obtain a temperature field distribution diagram of the fluid surface.

Abstract: A method for forming a semiconductor structure includes forming a gate electrode layer over a semiconductor substrate, forming a first spacer layer to cover a sidewall of the gate electrode layer, recessing the first spacer layer to expose an upper portion of the sidewall of the gate electrode layer, forming a metal material to cover an upper surface and the upper portion of the sidewall of the gate electrode layer; reacting a semiconductor material of the gate electrode layer with the metal material using an anneal process to form a silicide layer, and removing the metal material after the anneal process.

Abstract: A method of WDM-aware optical routing for on-chip devices is proposed, which is executed by a computer, the method comprising using the computer to perform the following steps of: performing a path separation to identify signal net candidates; performing a path clustering to find path clusters of the signal net candidates; performing an endpoint placement to find legal locations for WDM endpoints; and performing a pin-to-waveguide routing all nets to corresponding WDM waveguides.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

Abstract: A DHCP server implementation includes transmission of a DHCP packet from a virtual machine executing on a server node to a node agent executing on the server node, generation, by the node agent, of a DHCP response packet based on the DHCP packet and on DHCP information previously stored in a local memory of the server node, and transmission of the DHCP response packet from the node agent to the virtual machine. Neither the DHCP packet transmitted by the virtual machine nor the DHCP response packet are transmitted out of the server node.

Abstract: A method for cleaning a semiconductor substrate is provided. The method includes the steps of: applying a first agent onto a top surface of the semiconductor substrate while the semiconductor substrate is rotated at a first rotational frequency; immersing the semiconductor substrate in a second agent while rotating the semiconductor substrate at a second rotational frequency; and rotating the semiconductor substrate at a third rotational frequency while a third agent is introduced onto the top surface of the semiconductor substrate. The first rotational frequency may be greater than the third rotational frequency and the third rotational frequency is greater than the second rotational frequency. In some embodiments, the second rotational frequency is zero and the semiconductor substrate is held stationary during the immersing step.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

Abstract: A method for forming a semiconductor structure includes: providing a substrate; forming a stacked structure on the substrate; forming a barrier layer on a sidewall of the stacked structure; forming a first dielectric layer covering the barrier layer and the stacked structure; removing a portion of the first dielectric layer to expose an upper portion of the stacked structure; forming a metal layer covering the stacked structure and the first dielectric layer; performing an annealing process to react the metal layer with the stacked structure to form a metal silicide layer at the upper portion of the stacked structure; removing an unreacted portion of the metal layer; removing a portion of the barrier layer to form a recess above the barrier layer; and forming a second dielectric layer covering the metal silicide layer and the first dielectric layer to form air gaps on both sides of the stacked structure.

Abstract: A method for forming a semiconductor structure includes: providing a substrate; forming a stacked structure on the substrate; forming a barrier layer on a sidewall of the stacked structure; forming a first dielectric layer covering the barrier layer and the stacked structure; removing a portion of the first dielectric layer to expose an upper portion of the stacked structure; forming a metal layer covering the stacked structure and the first dielectric layer; performing an annealing process to react the metal layer with the stacked structure to form a metal silicide layer at the upper portion of the stacked structure; removing an unreacted portion of the metal layer; removing a portion of the barrier layer to form a recess above the barrier layer; and forming a second dielectric layer covering the metal silicide layer and the first dielectric layer to form air gaps on both sides of the stacked structure.

Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

Abstract: This disclosure provides isolated antibodies that bind specifically to CD27 with high affinity. The disclosure provides methods for treating a subject afflicted with a cancer comprising administering to the subject a therapeutically effective amount of an anti-CD27 antibody as monotherapy or in combination with a checkpoint inhibitor, such as an anti-PD-1, anti-PD-L1, or anti-CTLA-4 antibody.

Abstract: An inflation mechanism adapted to a robotic device is provided. The inflation mechanism includes a regulating unit and a control unit. The regulating unit includes an inflatable air bag, a pressure detecting unit and a pressure adjusting unit. The inflatable air bag is arranged on a body surface of the robotic device. The pressure detecting unit is coupled to the inflatable air bag for detecting an internal pressure of the inflatable air bag. The pressure adjusting unit is coupled to the inflatable air bag for adjusting the internal pressure of the inflatable air bag. The control unit is coupled to the regulating unit. The control unit processes a signal received from the pressure detecting unit, and determines and controls the pressure adjusting unit to adjust the internal pressure of the inflatable air bag according to a set condition.

Abstract: A memory device and a manufacturing method thereof are provided. The memory device includes a gate stacking structure, a first insulating layer, a second insulating layer and a first spacer. The gate stacking structure is disposed over a substrate. The first insulating layer covers a top surface and a sidewall of the gate stacking structure. The second insulating layer covers a surface of the first insulating layer. A top corner region of the gate stacking structure is covered by the first and second insulating layers. The first spacer is located on the sidewall of the gate stacking structure, and covers a surface of the second insulating layer. A topmost end of the first spacer is lower than a topmost surface of the second insulating layer.