Patents by Inventor Sheng YU

Sheng YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220183019
    Abstract: A method and system are provided for scheduling data transmission in a Multiple-Input Multiple-Output (MIMO) system. The MIMO system may comprise at least one MIMO transmitter and at least one MIMO receiver. Feedback from one or more receivers may be used by a transmitter to improve quality, capacity, and scheduling in MIMO communication systems. The method may include generating or receiving information pertaining to a MIMO channel metric and information pertaining to a Channel Quality Indicator (CQI) in respect of a transmitted signal; and sending a next transmission to a receiver using a MIMO mode selected in accordance with the information pertaining to the MIMO channel metric, and an adaptive coding and modulation selected in accordance with the information pertaining to the CQI.
    Type: Application
    Filed: February 23, 2022
    Publication date: June 9, 2022
    Inventors: Ming JIA, Jianming WU, Dong-Sheng YU, Peiying ZHU, Wen TONG
  • Patent number: 11334360
    Abstract: The present invention performs high-throughput disassembly for executable code comprising a plurality of instructions. An input of the executable code is received. Exhaustive disassembly is performed on the executable code to produce a set of exhaustively disassembled instructions. An instruction flow graph is constructed from the exhaustively disassembled instructions. Instruction embedding is performed on the exhaustively disassembled instructions to construct embeddings.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: May 17, 2022
    Assignees: DEEPBITS TECHNOLOGY INC., THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Xunchao Hu, Sheng Yu, Heng Yin
  • Publication number: 20220149141
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen
  • Patent number: 11327578
    Abstract: A control circuit for an input device including a micro-switch is provided. The control circuit includes an input circuit, a receiver circuit, a control unit, and a detecting unit. The input circuit includes a first contact and a second contact for electrically connecting to the micro-switch. The receiver circuit includes a third contact and a fourth contact for electrically connecting to the micro-switch. The control unit is electrically connected to the first contact and the third contact for providing an input signal via the first contact to the micro-switch and receiving a switching signal from the micro-switch via the third contact. The detecting unit detects a voltage of the second contact to generate a detecting signal. The control unit receives the detecting signal to determine a type of the micro-switch.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: May 10, 2022
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Kuo-En Lin, Shau-Yang Hsieh, Ming-Hsing Chuang, Sheng-Yu Wang, Chih-Yuan Lin, Shih-Hung Chou, Xin-Han Cai, I-Ting Hsieh
  • Publication number: 20220141971
    Abstract: A semiconductor device package includes a display device, an encapsulation layer disposed in direct contact with the display device, and a reinforced structure surrounded by the encapsulation layer. The reinforced structure is spaced apart from a surface of the display device. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Application
    Filed: January 11, 2022
    Publication date: May 5, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Yung I. YEH, Chang-Lin YEH, Sheng-Yu CHEN
  • Patent number: 11320747
    Abstract: Photolithography apparatus includes a radiation source, a mask to modify radiation from the radiation source so the radiation exposes photoresist layer disposed on a semiconductor substrate in patternwise manner, a wafer stage, and a controller. The wafer stage supports the semiconductor substrate. The controller determines target total exposure dose for the photoresist layer and target focus position for the photoresist layer; and controls exposure of first portion of the photoresist layer to first exposure dose of radiation at first focus position using first portion of the mask, moving the semiconductor substrate relative to the mask; and exposure of the first portion of the photoresist layer to second exposure dose of radiation using second portion of the mask at second focus position, and exposure of second portion of the photoresist layer to the second exposure dose at the second focus position using the first portion of the mask.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: May 3, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shinn-Sheng Yu, Ru-Gun Liu, Hsu-Ting Huang, Kenji Yamazoe, Minfeng Chen, Shuo-Yen Chou, Chin-Hsiang Lin
  • Patent number: 11312123
    Abstract: A vacuum lamination system includes a film supply assembly, a film collection assembly, a lower lamination body, an upper lamination body, an air extractor, a moving assembly and a cutting assembly. The lower lamination body includes a first casing base and a lower heating assembly vertically movable and disposed in the first casing base. The lower heating assembly carries and moves the substrate so that the substrate is substantially flush with a top surface of the first casing base or retracted into the first casing base. The upper lamination body is vertically movable and disposed above the lower lamination body and includes an upper casing and an upper heating assembly disposed on the upper casing. The air extractor is connected to the lower lamination body. The moving assembly changes a height of a portion of the film. The cutting assembly cuts a portion of the film laminated onto the substrate.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: April 26, 2022
    Assignee: ELEADTK CO., LTD.
    Inventors: Ching-Nan Chang, Sheng-Yu Lin, Ming-Chan Chen
  • Patent number: 11317384
    Abstract: To effectively and efficiently provide control information, a broadcast pointer channel (BPCH) may be used to identify the type and perhaps relative location of control information that is being provided in a given frame structure, such as a sub-frame, frame, or superframe. A sub-frame (or like framing entity, such a frame or superframe) may have a BPCH and a corresponding system control information segment in which control information may reside. The system control information segment may have any number of control information blocks, wherein each control information block that is present may correspond to a particular type of control information. The BPCH is used to identify the type of control information that is present in a corresponding system control information segment, and if needed or desired, the relative locations of the various control information.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 26, 2022
    Assignee: Apple Inc.
    Inventors: Mo-Han Fong, Hang Zhang, Sophie Vrzic, Robert Novak, Jun Yuan, Dong-Sheng Yu
  • Patent number: 11315896
    Abstract: A pillar structure, and a method of forming, for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: April 26, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tin-Hao Kuo, Chen-Shien Chen, Mirng-Ji Lii, Chen-Hua Yu, Sheng-Yu Wu, Yao-Chun Chuang
  • Patent number: 11312562
    Abstract: A heat insulating container includes a bottom box and a surrounding wall surrounding the bottom box. A top portion of the bottom box is open and connected with the surrounding wall. An inner space of the surrounding wall is connected with an inner space of the bottom box, an opening is defined by a top edge of the surrounding wall, a handle portion is downward extended from an external surface of a junction between the bottom box and the surrounding wall, the handle portion and the bottom box are arranged at interval and a rubber strip is arranged wrapping the handle portion. Thereby the user is avoided from directly contacting with the bottom box. Therefore, the heat insulating container could be immediately taken out of a microwave oven after heater by the microwave oven.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 26, 2022
    Assignee: FREE-FREE INDUSTRIAL CORP
    Inventor: Sheng-Yu Liu
  • Patent number: 11315513
    Abstract: A driving circuit for display panel is provided. Wherein, a first and a second power supply circuits produce a first and a second supply voltages. The electric charge provided by the second power supply circuit is less than that provided by the first power supply circuit. A plurality of drivers include a plurality of first power input terminals and a plurality of second power input terminals. The first power input terminals are coupled to the first power supply circuit and receives the first supply voltage. The second power input terminals are coupled to the second power supply circuit and receives the second supply voltage. The drivers increase the voltage levels of a plurality of gate signals in a voltage rising period according to the first supply voltage. The drivers hold the voltage levels of gate signals in a voltage holding period according to the second supply voltage.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 26, 2022
    Assignee: Sitronix Technology Corp.
    Inventors: Kuan-Chao Liao, Sheng-Yu Lin
  • Publication number: 20220107317
    Abstract: Provided are methods and compositions for the diagnosis and treatment of COVID-19, a disease caused by SARS-CoV-2 infection. More specifically, peptides that bind to SARS-CoV-2 are provided for use as diagnostic and therapeutic compositions in diagnosis, treatment and prevention of individuals contracting, or in danger of contracting COVID-19.
    Type: Application
    Filed: October 1, 2021
    Publication date: April 7, 2022
    Inventors: Chia-Ching Chang, Chia-Yu Chang, Shin-Ru Shih, Sheng-Yu Huang
  • Patent number: 11295056
    Abstract: A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape pattern associated with an opening. The method includes defining a polygon having a plurality of vertices on the disk shape pattern. The plurality of vertices coincide with a boundary of the disk shape pattern and the polygon is an initial layout pattern of the opening. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the opening onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the opening is generated.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shinn-Sheng Yu
  • Publication number: 20220102453
    Abstract: A semiconductor device package includes a display device, an electronic module and a conductive adhesion layer. The display device includes a first substrate and a TFT layer. The first substrate has a first surface and a second surface opposite to the first surface. The TFT layer is disposed on the first surface of the first substrate. The electronic module includes a second substrate and an electronic component. The second substrate has a first surface facing the second surface of the first substrate and a second surface opposite to the first surface. The electronic component is disposed on the second surface of the second substrate. The conductive adhesion layer is disposed between the first substrate and the second substrate.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Ming-Hung CHEN, Sheng-Yu CHEN, Chang-Lin YEH, Yung-I YEH
  • Patent number: 11289394
    Abstract: A semiconductor package includes a substrate having a first side and a second side opposite to the first side, a first type semiconductor die disposed on the first side of the substrate, a first compound attached to the first side and encapsulating the first type semiconductor die, and a second compound attached to the second side, causing a stress with respect to the first type semiconductor die in the first compound. A method for manufacturing the semiconductor package described herein is also disclosed.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 29, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Yu Chen, Chang-Lin Yeh, Ming-Hung Chen
  • Patent number: 11291017
    Abstract: A method and system are provided for scheduling data transmission in a Multiple-Input Multiple-Output (MIMO) system. The MIMO system may comprise at least one MIMO transmitter and at least one MIMO receiver. Feedback from one or more receivers may be used by a transmitter to improve quality, capacity, and scheduling in MIMO communication systems. The method may include generating or receiving information pertaining to a MIMO channel metric and information pertaining to a Channel Quality Indicator (CQI) in respect of a transmitted signal; and sending a next transmission to a receiver using a MIMO mode selected in accordance with the information pertaining to the MIMO channel metric, and an adaptive coding and modulation selected in accordance with the information pertaining to the CQI.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: March 29, 2022
    Assignee: BlackBerry Limited
    Inventors: Wen Tong, Ming Jia, Jianming Wu, Dong-Sheng Yu, Peiying Zhu
  • Publication number: 20220077094
    Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad over the semiconductor substrate, a conductive bump, a conductive cap over the conductive bump, and a passivation layer. The conductive pad is over the semiconductor substrate. The conductive bump is over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall. The conductive cap is over the conductive bump. The passivation layer is over the semiconductor substrate and laterally surrounds the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of conductive cap.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Yu WU, Ching-Hui CHEN, Mirng-Ji LII, Kai-Di WU, Chien-Hung KUO, Chao-Yi WANG, Hon-Lin HUANG, Zi-Zhong WANG, Chun-Mao CHIU
  • Publication number: 20220074939
    Abstract: A method for determining immune competence against severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) includes obtaining a blood sample from a subject in need thereof, detecting, in the blood sample, levels of binding antibodies against SARS-CoV-2 spike S1 protein and its receptor binding domain (RBD), and calculating a weighted value using a regression model. Another method for determining immune competence against SARS-CoV-2 is also disclosed.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 10, 2022
    Inventors: Shin-Ru SHIH, Kuan-Ting LIU, Guang-Wu CHEN, Chung-Guei HUANG, Kar-Yee YU, Hou-Chen LEE, Peng-Nien HUANG, Yu-Nong GONG, Rei-Lin KUO, Chih-Ching WU, Yu-An KUNG, Sheng-Yu HUANG
  • Publication number: 20220055797
    Abstract: A collapsible container comprises a bottom plate, a first ring, a second ring, a spring, a cladding layer, and at least two fastening parts. The first ring is disposed around the bottom plate. The caliber of the second ring is smaller than that of the first ring. The two ends of the spring are respectively connected to the first ring and the second ring to maintain a distance between the first ring and the second ring. When the spring is compressed, the second ring can be moved and be stored in an inner side of the first ring. The cladding layer clads the bottom plate, the first ring, the second ring and the spring. The fastening parts are disposed symmetrically on an outer side of the first ring for fastening the second ring when the second ring is moved to the inside of the first ring.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Inventor: Sheng-Yu Liu
  • Patent number: 11239305
    Abstract: A display device includes a semiconductor substrate, an isolation layer, a light-emitting layer and a second electrode. The semiconductor substrate has a pixel region and a peripheral region located around the pixel region. The semiconductor substrate includes first electrodes and a driving element layer. The first electrodes are disposed in the pixel region and the first electrodes are electrically connected to the driving element layer. The isolation layer is disposed on the semiconductor substrate. The isolation layer includes a first isolation pattern disposed in the peripheral region, and the first isolation pattern has a first side surface and a second side surface opposite to the first side surface. The light-emitting layer is disposed on the isolation layer and the first electrodes, and covers the first side surface and the second side surface of the first isolation pattern. The second electrode is disposed on the light-emitting layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: February 1, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Yu Wu, Mirng-Ji Lii, Shang-Yun Tu, Ching-Hui Chen