Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.

Abstract: A method for fabricating a semiconductor device includes the steps of providing a substrate having a high electron mobility transistor (HEMT) region and a capacitor region, forming a first mesa isolation on the HEMT region and a second mesa isolation on the capacitor region, forming a HEMT on the first mesa isolation, and then forming a capacitor on the second mesa isolation.

Abstract: The invention discloses a memory fabrication method. The memory fabrication method includes forming a plurality of gate electrode lines to respectively form a plurality of gates of a plurality of data storage cells, and forming a plurality of conductive lines. The plurality of data storage cells are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines. Each of the plurality of conductive lines at least partially overlaps the two gate electrode lines of the plurality of gate electrode lines.

Abstract: A magnetoresistive random access memory (MRAM) includes a first transistor and a second transistor on a substrate, a source line coupled to a first source/drain region of the first transistor, and a first metal interconnection coupled to a second source/drain region of the first transistor. Preferably, the first metal interconnection is extended to overlap the first transistor and the second transistor and the first metal interconnection further includes a first end coupled to the second source/drain region of the first transistor and a second end coupled to a magnetic tunneling junction (MTJ).

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

Abstract: An integrated circuit chip has an active surface and a chip pad arrangement on the active surface. The chip pad arrangement includes four pairs of chip pads arranged in two rows along a side edge of the active surface. Two pairs of chip pads are a first transmission differential pair chip pad and a first reception differential pair chip pad respectively. Positions of the two pairs of chip pads are not adjacent to each other and are in different rows. The other two pairs of chip pads are a second transmission differential chip pad and a second reception differential chip pad respectively. Positions of the other two pairs of chip pads are not adjacent to each other and are in different rows. In addition, a package substrate corresponding to the integrated circuit chip and an electronic assembly including the package substrate and the integrated circuit chip are also provided.

Abstract: A multilayer-type on-chip inductor includes a first winding portion arranged in an inter-metal dielectric (IMD) layer, which includes first and second semi-circular stacking layers arranged from inside to outside and in concentricity. A second winding portion includes third and fourth semi-circular stacking layers arranged symmetrically with the first semi-circular stacking layer and the second semi-circular stacking layer, respectively, with respect to a symmetry axis. A conductive branch layer is disposed in an insulating redistribution layer over the IMD layer. The first, second, third, and fourth semi-circular stacking layers each include an uppermost trace layer and a next uppermost trace layer vertically stacked under the uppermost trace layer.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer correspondingly formed below the first spiral trace layer, wherein the inter-metal dielectric layer has a separating region to divide the second spiral trace layer into a plurality of line segments, and wherein each of a plurality of first slit openings and each of a plurality of second slit openings pass through a corresponding line segment, and extend in an extending direction of a length of the corresponding line segment.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer. The inter-metal dielectric layer has a separating region to divide the second spiral trace layer into line segments. First slit openings each passes through a corresponding line segment, and extends in an extending direction of a length of the corresponding line segment.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric layer, a first spiral trace layer disposed in the insulating redistribution layer, and a second spiral trace layer disposed in the inter-metal dielectric layer and correspondingly formed below the first spiral trace layer. The inter-metal dielectric layer has a separating region to divide the second spiral trace layer into line segments. First slit openings each passes through a corresponding line segment, and extends in an extending direction of a length of the corresponding line segment.

Abstract: A multilayer-type on-chip inductor with a conductive structure includes an insulating redistribution layer disposed on an inter-metal dielectric (IMD) layer, and first and second winding portions symmetrically arranged in the IMD layer and the insulating redistribution layer with respect to a symmetrical axis. The first and second winding portions each includes at least first and second semi-circular stacking layers arranged from the inside to the outside and in concentricity. The first and second semi-circular stacking layers each has a first trace layer in the insulating redistribution layer and a second trace layer in the IMD layer and correspondingly formed below the first trace layer. A first slit opening passes through the second trace layer and extends in the extending direction of the length of the second trace layer.

Abstract: An on-chip inductor structure includes first and second winding portions symmetrically arranged in an insulating layer by a symmetrical axis. Each of the first and second winding portions includes first and second semi-circular conductive lines concentrically arranged from the inside to the outside. First and second input/output conductive portions are disposed in the insulating layer along the extending direction of the symmetrical axis, to respectively and electrically couple the first ends of the outermost semi-circular conductive lines. A conductive branch structure is disposed in the insulating layer along the symmetrical axis and between the first and second input/output conductive portions, and electrically coupled to first ends of the innermost semi-circular conductive lines. The conductive branch structure has a grounded first end and a second end is electrically coupled to a circuit and is opposite the first end of the conductive branch structure.

Abstract: An on-chip inductor structure includes first and second winding portions symmetrically arranged in an insulating layer by a symmetrical axis. Each of the first and second winding portions includes first and second semi-circular conductive lines concentrically arranged from the inside to the outside. First and second input/output conductive portions are disposed in the insulating layer along the extending direction of the symmetrical axis, to respectively and electrically couple the first ends of the outermost semi-circular conductive lines. A conductive branch structure is disposed in the insulating layer along the symmetrical axis and between the first and second input/output conductive portions, and electrically coupled to first ends of the innermost semi-circular conductive lines. The conductive branch structure has a grounded first end and a second end is electrically coupled to a circuit and is opposite the first end of the conductive branch structure.

Abstract: An integrated circuit chip has an active surface and a chip pad arrangement on the active surface. The chip pad arrangement includes four pairs of chip pads arranged in two rows along a side edge of the active surface. Two pairs of chip pads are a first transmission differential pair chip pad and a first reception differential pair chip pad respectively. Positions of the two pairs of chip pads are not adjacent to each other and are in different rows. The other two pairs of chip pads are a second transmission differential chip pad and a second reception differential chip pad respectively. Positions of the other two pairs of chip pads are not adjacent to each other and are in different rows. In addition, a package substrate corresponding to the integrated circuit chip and an electronic assembly including the package substrate and the integrated circuit chip are also provided.

Abstract: A paddle card includes a circuit board, a pad group and ground planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads and the pair of lower differential pads are corresponding to each other respectively and configured up and down. The ground planes are spaced at intervals between the upper surface and the lower surface. The ground plane below the pair of upper differential pads has an opening corresponding thereto. A portion of the at least one ground plane between the pair of upper differential pads and the pair of lower differential pads is solid as a shield.

Abstract: A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads is respectively configured corresponding to the pair of lower differential pads in an up and down manner. The first to fourth shielding planes are stacked at intervals between the upper and lower surfaces in sequence. An orthogonal projection of a second opening of the second shielding plane on a geometric plane that a pair of third openings of the third shielding plane is located in is separate from the pair of third openings.

Abstract: A semiconductor device includes an insulating layer disposed over a substrate, wherein the insulating layer has a center region. A first winding portion and a second winding portion are electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside. A first extending conductive line and a second extending conductive line partially surround the first extending conductive line, and are disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line. A third extending conductive line is disposed in a second level of the insulating layer and surrounding the center region.

Abstract: A semiconductor device includes an insulating layer disposed over a substrate, wherein the insulating layer has a center region. A first winding portion and a second winding portion are electrically connected to the first winding portion, disposed in a first level of the insulating layer and surrounding the center region, wherein each of the first winding portion and the second winding portion comprises a plurality of conductive lines arranged from the inside to the outside. A first extending conductive line and a second extending conductive line partially surround the first extending conductive line, and are disposed in the first level of the insulating layer, wherein the first winding portion and the second winding portion surround the first extending conductive line and the second extending conductive line. A third extending conductive line is disposed in a second level of the insulating layer and surrounding the center region.

Abstract: A semiconductor device includes first and second winding portions disposed in a first level of an insulating layer and surrounding a center region thereof. Each of the winding portions includes conductive lines arranged from the inside to the outside. First and second extending conductive lines are disposed in the first level of the insulating layer. A third extending conductive line is disposed in a second level of the insulating layer. The first extending conductive line is coupled between the innermost conductive line of the second winding and the third extending conductive line. The second extending conductive line is coupled between the innermost conductive line of the first winding portion and the third extending conductive line. The first extending conductive line and the third extending conductive line coupled thereto are arranged in a helix or a spiral spatial configuration.