Patents by Inventor Sheng-Yuan Lee

Sheng-Yuan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7504922
    Abstract: An embedded inductor suitable for a wiring board is provided. The wiring board comprises a plurality of patterned conductive layers, at least an insulating layer, and a plurality of conductive vias. The insulating layer is disposed between the neighboring patterned conductive layers. Two of the patterned conductive layers are electrically connected to each other through one of the conductive vias. The embedded inductor comprises a conductive spiral structure and at least an insulating portion. The insulating portion is disposed in the insulating layer and adjacent to the conductive spiral structure. The dielectric constant of the insulating portion is lower than that of the insulating layer. A parasitic capacitance value generated from the operation of the embedded inductor of the present invention is lower. Accordingly, the resonant frequency and the quality factor of the embedded inductor are effectively improved.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: March 17, 2009
    Assignee: VIA Technologies, Inc.
    Inventor: Sheng-Yuan Lee
  • Publication number: 20090045903
    Abstract: An inductor structure including a coil layer and at least a gain lead is disclosed. The coil layer is disposed over a substrate and has a plurality of coil turns, wherein one of the coil turns is grounded. The gain lead is disposed under at least one of the inner side and the outer side of the grounded coil turn and is electrically connected in parallel to the grounded coil turn. The width of the gain lead is less than the width of the grounded coil turn.
    Type: Application
    Filed: November 7, 2007
    Publication date: February 19, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Hsiao-Chu Lin, Sheng-Yuan Lee
  • Patent number: 7489218
    Abstract: An inductor structure, including a winding turn layer and a shielding layer, is provided. The winding turn layer is disposed above a substrate. The winding turn layer has a plurality of turns, in which one of the turns is grounded. The shielding layer is disposed between the winding turn layer and the substrate at the projection of the grounded turn. At least parts of the winding turn layer except the grounded turn thereof are projected onto the shielding layer. The shielding layer is coupled to the grounded turn in parallel.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: February 10, 2009
    Assignee: Via Technologies, Inc.
    Inventor: Sheng-Yuan Lee
  • Patent number: 7485966
    Abstract: The invention discloses a via connection structure with compensative area on a reference plane. The substrate has several conductive layers isolated by the insulation layers. When two conductive lines formed on different conductive layers where a reference plane is sandwiched in, these two conductive lines are not electrical connected because of the insulation layers. Furthermore, a via connection structure is common used to connect these two conductive lines. When a non-conductive area, i.e. the compensative area, on the reference plane is overlapped with a portion of one conductive line and is close to the via connection structure, it compensates the capacitive effect of the via connection structure. By this compensative area and the variety of the via connection structure, the vertical connection between different layers has a well impedance-matched condition and transmits the signal correctly.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: February 3, 2009
    Assignee: VIA Technologies, Inc.
    Inventors: Shin-Shing Jiang, Sheng-Yuan Lee
  • Publication number: 20090020877
    Abstract: A transmission line structure includes a routing trace, a doped region and a first guard trace. The routing trace is disposed over a substrate. The doped region is disposed in the substrate and the projection of at least the partial routing trace falls within the doped region. The first guard trace is located over the substrate and disposed with a space from the routing trace, wherein the first guard trace is grounded and electrically coupled with the doped region. In addition, the conductivity of the first guard trace is higher than the conductivity of the doped region.
    Type: Application
    Filed: September 25, 2007
    Publication date: January 22, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Sheng-Yuan Lee
  • Patent number: 7477125
    Abstract: A symmetrical inductor device arranged on a substrate is provided. The inductor device comprises first and second winding portions symmetrically arranged on an insulating layer on the substrate, in which each winding portion comprises first and second semi-circular conductive traces concentrically arranged from the outside to the inside, and each semi-circular conductive trace has a first end and a second end. Upper and lower cross-connections are crossly and respectively connected to the corresponding second ends of the first and second semi-circular conductive traces. First and second interconnections are respectively disposed in the insulating layer under the semi-circular conductive traces connected to both ends of the upper cross-connection, in which each interconnection comprises at least one conductive layer and a plurality of conductive plugs electrically connected between the conductive layer and the corresponding semi-circular conductive trace.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: January 13, 2009
    Assignee: Via Technologies, Inc.
    Inventors: Hsiao-Chu Lin, Sheng-Yuan Lee
  • Patent number: 7443272
    Abstract: A signal transmission structure is at the edge of a circuit board, and the circuit board is connected with a coaxial cable connector through the signal transmission structure. The coaxial cable connector has a signal pin and a plurality of supporting pins for clipping the circuit board. The signal transmission structure includes a reference plane and a conductive layer. The reference plane with a non-conductive area is inside the circuit board. The conductive layer is disposed on the surface of the circuit board and above one side of the reference plane. The conductive layer includes a signal pad and a signal line. The signal line is connected with the signal pad, and the signal pad is further connected with the signal pin of the coaxial connector. The projections of the signal pad and the portion of the signal line on the reference plane are in the non-conductive area.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: October 28, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Shin-Shing Jiang, Sheng-Yuan Lee
  • Patent number: 7436268
    Abstract: A signal transmission structure for connecting a coaxial cable connector is provided. The coaxial cable connector has a signal pin. The signal transmission structure includes a reference plane and a conductive layer, and the conductive layer is located on one side of the reference plane. Moreover, the conductive layer includes a signal perforated pad, a first line segment, a second line segment, and a compensation pad. The signal pin is suitable for threading the signal perforated pad. The first line segment is connected to the signal perforated pad, and the compensation pad is connected between the first line segment and the second line segment.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 14, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Shin-Shing Jiang, Sheng-Yuan Lee
  • Patent number: 7420451
    Abstract: A symmetrical differential inductor including a first spiral conducting wire and a second spiral conducting wire is provided. The first spiral conducting wire has a first end and a second end, and the second end whirls in spiral fashion towards a central portion of a spiral structure of the first spiral conducting wire. The second spiral conducting wire and the first spiral conducting wire are interwound with each other and symmetrical to a symmetrical plane. The second spiral conducting wire has a third end and a fourth end, and the fourth end whirls in spiral fashion towards a central portion of a spiral structure of the second spiral conducting wire and is connected to the second end of the first spiral conducting wire. When the first spiral conducting wire and the second spiral conducting wire having the same distance from the substrate are staggered, they extend towards the substrate.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: September 2, 2008
    Assignee: VIA Technologies Inc.
    Inventor: Sheng-Yuan Lee
  • Patent number: 7420452
    Abstract: An inductor structure disposed over a substrate includes a first spiral coil, a second spiral coil and at least a gain pattern. The first spiral coil includes first conducting wires and first connection leads, wherein each first connection lead connects two adjacent first conducting wires. The second spiral coil includes second conducting wires and second connection leads, wherein each second connection lead connects two adjacent second conducting wires. The second spiral coil and the first spiral coil are symmetrically disposed about a plane of symmetry and in series connection to form a spiral coil structure with 2N turns, wherein N is a positive integral, and are spaced from the substrate by different heights to form 2N?1 interlaced zones. The gain pattern is disposed under the first connection lead at the (2N?1)th interlaced zone counted from the most-outer turn up and electrically connected to the corresponding first connection lead.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: September 2, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Sheng-Yuan Lee, Hsiao-Chu Lin
  • Publication number: 20080203580
    Abstract: A semiconductor chip including a substrate, a metal interconnection structure and a circuit region is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring, wherein the guard ring comprises a plurality of individual segments, and the individual segments are individually and electrically coupled to the ground contacts. The circuit region disposed on the substrate. A projection of the dielectric ring on the substrate surface surrounds a projection of the circuit region on the substrate surface, and the projection of the guard ring on the substrate surface surrounds that of the dielectric ring and that of the circuit region on the substrate surface.
    Type: Application
    Filed: May 9, 2008
    Publication date: August 28, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Sheng-Yuan Lee
  • Publication number: 20080191829
    Abstract: An inductor structure including a first winding turn and a second winding turn is provided. The first winding turn is disposed above a substrate. The second winding turn is disposed between the first winding turn and the substrate. One end of the second winding turn is grounded, and the other end of the second winding turn and the first winding turn are electrically connected in series. The first winding turn and the second winding turn form a three-dimensional helix structure above the substrate. The width of the second winding turn is greater than that of the first winding turn, and furthermore, the first winding turn is projected onto the second winding turn.
    Type: Application
    Filed: April 30, 2007
    Publication date: August 14, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Sheng-Yuan Lee
  • Patent number: 7405483
    Abstract: A circuit board assembled with an electronic package having a first and a second inner leads is provided. The first inner lead has a first and a second ends. The circuit board includes an insulating layer, a first pad, a second pad, an extension portion, a conductive via, and a ground layer. The first and the second pads are disposed on the insulating layer. The first end of the first inner lead is electrically connected to the second pad. The extension portion disposed on the insulating layer is electrically connected to the first pad and extends to the position under the second end of the first inner lead. The conductive via passing through the insulating layer is electrically connected to the extension portion and under the second end of the first inner lead. The ground layer disposed on the insulating layer is electrically connected to the conductive via.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: July 29, 2008
    Assignee: VIA Technologies, Inc.
    Inventors: Sheng-Yuan Lee, Hsiao-Chu Lin
  • Publication number: 20080174394
    Abstract: A symmetrical differential inductor including a first spiral conducting wire and a second spiral conducting wire is provided. The first spiral conducting wire has a first end and a second end, and the second end whirls in spiral fashion towards a central portion of a spiral structure of the first spiral conducting wire. The second spiral conducting wire and the first spiral conducting wire are interwound with each other and symmetrical to a symmetrical plane. The second spiral conducting wire has a third end and a fourth end, and the fourth end whirls in spiral fashion towards a central portion of a spiral structure of the second spiral conducting wire and is connected to the second end of the first spiral conducting wire. When the first spiral conducting wire and the second spiral conducting wire having the same distance from the substrate are staggered, they extend towards the substrate.
    Type: Application
    Filed: March 26, 2007
    Publication date: July 24, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: SHENG-YUAN LEE
  • Publication number: 20080174395
    Abstract: An inductor structure, including a winding turn layer and a shielding layer, is provided. The winding turn layer is disposed above a substrate. The winding turn layer has a plurality of turns, in which one of the turns is grounded. The shielding layer is disposed between the winding turn layer and the substrate at the projection of the grounded turn. At least parts of the winding turn layer except the grounded turn thereof are projected onto the shielding layer. The shielding layer is coupled to the grounded turn in parallel.
    Type: Application
    Filed: June 29, 2007
    Publication date: July 24, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Sheng-Yuan Lee
  • Publication number: 20080169895
    Abstract: A spiral inductor with a multi-trace structure having an insulating layer disposed on a substrate. A first spiral conductive trace with multiple turns is disposed on the insulating layer, wherein the outermost turn and the innermost turn of the first spiral conductive trace have a first end and a second end, respectively, and one of the first and second ends is connected to ground. A second spiral conductive trace with a single turn is disposed on the insulating layer and adjacent to the first spiral conductive trace, wherein the second spiral conductive trace is electrically connected to the turn that is connected to the ground and belongs to the first spiral conductive trace. The first spiral conductive trace has a relative outside and a relative inside, wherein the end of the first spiral conductive trace connected to ground and the second spiral conductive trace are located at different sides respectively.
    Type: Application
    Filed: July 6, 2007
    Publication date: July 17, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Sheng-Yuan Lee
  • Patent number: 7382219
    Abstract: An inductor structure including a first helix winding, a second helix winding, and a shielding structure is provided. The first helix winding has a first exterior wire connecting with a first interior wire in series. The second helix winding and the first helix winding are intercoiled about a symmetric plane. The second helix winding has a second exterior wire connecting with a second interior wire in series and connects with the first interior wire. The shielding structure includes a first shielding layer disposed between the first exterior wire and the substrate corresponding to a projection of the first exterior wire and a second shielding layer disposed between the second exterior wire and the substrate corresponding to a projection of the second exterior wire. The first shielding layer and the second shielding layer are grounded individually, and are in symmetry about the symmetric plane.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: June 3, 2008
    Assignee: VIA Technologies, Inc.
    Inventor: Sheng-Yuan Lee
  • Patent number: 7378743
    Abstract: A circuit board suitable for being electrically connected to a chip package is provided. The chip package has a chip pad and a plurality of inner leads. The circuit board includes at least one patterned conductive layer and at least one insulating layer. The patterned conductive layer has at least one first pad and at least one second pad. The first pad has an extension part and is suitable for being electrically connected to the chip pad. The second pad is suitable for being electrically connected to one end of at least one of the inner leads, while the other end of the inner lead suitable for being electrically connected to the second pad has a projection at least partially overlapping the extension part on the patterned conductive layer. Moreover, the patterned conductive layer is disposed outside the insulating layer.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: May 27, 2008
    Assignee: VIA Technologies, Inc.
    Inventor: Sheng-Yuan Lee
  • Publication number: 20080111220
    Abstract: A circuit board assembled with an electronic package having a first and a second inner leads is provided. The first inner lead has a first and a second ends. The circuit board includes an insulating layer, a first pad, a second pad, an extension portion, a conductive via, and a ground layer. The first and the second pads are disposed on the insulating layer. The first end of the first inner lead is electrically connected to the second pad. The extension portion disposed on the insulating layer is electrically connected to the first pad and extends to the position under the second end of the first inner lead. The conductive via passing through the insulating layer is electrically connected to the extension portion and under the second end of the first inner lead. The ground layer disposed on the insulating layer is electrically connected to the conductive via.
    Type: Application
    Filed: January 18, 2007
    Publication date: May 15, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Sheng-Yuan Lee, Hsiao-Chu Lin
  • Patent number: 7361981
    Abstract: A pad layout suitable for being applied on a metal interconnection structure of an integrated circuit chip is provided. The pad layout includes a first signal pad, a second signal pad, a first non-signal pad, a second non-signal pad, a first trace, a second trace, a first guard ring and a second guard ring. The second signal pad is located adjacent to the first signal pad. The first non-signal pad is located adjacent to the first signal pad. The second signal pad is located adjacent to the second signal pad. The first guard ring surrounds the first signal pad and is connected to the first non-signal pad through the first trace. The second guard ring surrounds the second signal pad and is connected to the second non-signal pad through the first trace.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: April 22, 2008
    Assignee: VIA Technologies, Inc.
    Inventor: Sheng-Yuan Lee