Abstract: A paddle card includes a circuit board, a pad group and first to fourth shielding planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads is respectively configured corresponding to the pair of lower differential pads in an up and down manner. The first to fourth shielding planes are stacked at intervals between the upper and lower surfaces in sequence. An orthogonal projection of a second opening of the second shielding plane on a geometric plane that a pair of third openings of the third shielding plane is located in is separate from the pair of third openings.

Abstract: A semiconductor device includes first and second winding portions disposed in a first level of an insulating layer and surrounding a center region thereof. Each of the winding portions includes conductive lines arranged from the inside to the outside. First and second extending conductive lines are disposed in the first level of the insulating layer. A third extending conductive line is disposed in a second level of the insulating layer. The first extending conductive line is coupled between the innermost conductive line of the second winding and the third extending conductive line. The second extending conductive line is coupled between the innermost conductive line of the first winding portion and the third extending conductive line. The first extending conductive line and the third extending conductive line coupled thereto are arranged in a helix or a spiral spatial configuration.

Abstract: A transmittal system including an extension device, a connection device, and an impedance device is disclosed. The extension device includes a first connection port and is coupled to a peripheral device. The connection device includes a second connection port and a third connection port. The second connection port is coupled to the first connection port. The third connection port is coupled to an electronic device. The impedance device connects at least one of the first, the second and the third connection ports to ground.

Abstract: A paddle card includes a circuit board, a pad group and ground planes. The circuit board has an upper surface and a lower surface opposite to each other. The pad group is adapted to connect wires of a cable or terminals of a plug, and includes a pair of upper differential pads on the upper surface and a pair of lower differential pads on the lower surface. The pair of upper differential pads and the pair of lower differential pads are corresponding to each other respectively and configured up and down. The ground planes are spaced at intervals between the upper surface and the lower surface. The ground plane below the pair of upper differential pads has an opening corresponding thereto. A portion of the at least one ground plane between the pair of upper differential pads and the pair of lower differential pads is solid as a shield.

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines.

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate; a device region formed in the semiconductor substrate; at least a conducting pad disposed over a surface of the semiconductor substrate; a protection plate disposed over the surface of the semiconductor substrate; and a spacer layer disposed between the surface of the semiconductor substrate and the protection plate, wherein the protection plate and the spacer layer surround a cavity over the device region, the spacer layer has an outer side surface away from the cavity, and the outer side surface of the spacer layer is not a cutting surface.

Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern and the second metal pattern. The third metal pattern is electrically grounding. An inductor is disposed over the third metal pattern.

Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern, and the second metal pattern. The third metal pattern is electrically grounded. An inductor is disposed over the third metal pattern.

Abstract: A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.

Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern and the second metal pattern. The third metal pattern is electrically grounding. An inductor is disposed over the third metal pattern.

Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a substrate. A first capacitor is disposed on the substrate. A first metal pattern is coupled to a first electrode of the first capacitor. A second metal pattern is coupled to a first electrode of the second capacitor. A third metal pattern is disposed over the first and second metal patterns. The third metal pattern covers the first capacitor, the first metal pattern, and the second metal pattern. The third metal pattern is electrically grounded. An inductor is disposed over the third metal pattern.

Abstract: A through-hole layout structure is suitable for a circuit board. The through-hole layout structure includes a pair of first differential through-holes, a pair of second differential through-holes, a first ground through-hole, a second ground through-hole, and a third ground through-hole, which are all arranged on a first line. The first ground through-hole is located between the pair of first differential through-holes and the pair of second differential through-holes. The pair of first differential through-holes is located between the first ground through-hole and the second ground through-hole. The pair of second differential through-holes is located between the first ground through-hole and the third ground through-hole.

Abstract: A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.

Abstract: A through-hole layout structure is suitable for a circuit board. The through-hole layout structure includes a pair of first differential through-holes, a pair of second differential through-holes, a first ground through-hole, a second ground through-hole, and a third ground through-hole, which are all arranged on a first line. The first ground through-hole is located between the pair of first differential through-holes and the pair of second differential through-holes. The pair of first differential through-holes is located between the first ground through-hole and the second ground through-hole. The pair of second differential through-holes is located between the first ground through-hole and the third ground through-hole.

Abstract: A circuit layout structure is suitable for a circuit board and includes following components. A first differential pair and a second differential pair respectively extend from the inside of a chip area of the circuit board to the outside of the chip area through a first patterned conductive layer of the circuit board, and respectively extend between the chip area and a port area of the circuit board through a second patterned conductive layer of the circuit board. A third differential pair extends from the chip area to the port area through the first patterned conductive layer. A first ground plane is constituted by the first patterned conductive layer. Orthogonal projections of the first differential pair and the second differential pair on the second patterned conductive layer overlap the first ground plane.

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines.

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines.

Abstract: An electronic device including an electronic unit and a cable assembly is provided. The cable assembly includes a first connector module, a second connector module, and a cable connecting between the first and the second connector modules. The first connector module detachably connected to the electronic device includes a serial advanced technology attachment (SATA) connector and a connector with at least four terminals.

Abstract: An active optical cable has a connector containing an electrical-to-optical and optical-to-electrical (EO/OE) conversion processing chip. The EO/OE conversion processing chip has a TXin+ pin and a TXin? pin to be coupled to a TX+ terminal and a TX? terminal of an USB connector of an apparatus. The pair of pins TXin+ and TXin?, for a differential transmission signal, are provided base on a common mode impedance structure, to charge capacitors carried by the TX+ and TX? terminals and, according to the charging status of the capacitors, it is determined whether the active optical cable is connected to the apparatus.

Abstract: A transmittal system including an extension device, a connection device, and an impedance device is disclosed. The extension device includes a first connection port and is coupled to a peripheral device. The connection device includes a second connection port and a third connection port. The second connection port is coupled to the first connection port. The third connection port is coupled to an electronic device. The impedance device connects at least one of the first, the second and the third connection ports to ground.