Abstract: A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2.

Abstract: The present invention provides an ESD protection device with isolated islands and an n well. At least one of the isolated islands has an end apart from the boundary of a drain diffusion region of the ESD protection device, to form a gap between. The n well overlaps with the isolated islands and is kept at least a designated distance away from a channel region of the ESD protection device. An interlocked structure of isolated islands is also provided in this invention to direct ESD current flowing forward and backward to the channel region of the ESD protection device, thereby increasing the distributed resistance of the drain diffusion region. Several benefits, such as lower drain capacitance, lower standby power consumption and a wider range of adjustable resistance, are achieved.

Abstract: A method of processing a partially defective memory for loading a machine code program into a memory device that includes at least one defective memory cell. At first the machine code program is scanned. In addition, a movable code block between two break points, which is ready to be loaded to the defective memory cell of the memory device, is determined. Then the block code is moved to a memory space between a first address and a second address in which there is no defective memory cell. Finally, the moved code block should be linked in the execution sequence with the unmoved portion of the machine code program and the addressing references correlated between the moved code block and the unmoved portion of the machine code program should be modified is and corrected. The resulting machine code program can be properly loaded and executable.

Abstract: An electrostatic discharge (ESD) protection device has a semiconductor bulk of a first conductivity type, a first doped region of a second conductivity type formed in the semiconductor bulk, a second doped region of a second conductivity type formed in the semiconductor bulk, a channel region formed between the first doped region and the second doped region, a plurality of contacts formed on the first doped region, and a well of the second conductivity type formed in the semiconductor bulk and positioned between the channel and the contacts.

Abstract: A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2.

Abstract: An early triggered MOSFET ESD protection circuit based on reduction of the trigger voltage is described. A transient negative voltage is generated and applied to a gate of a MOSFET during a positive ESD event. The instant invention improves ESD performance, and is particularly useful for thin gate oxide of 40 Å and less.

Abstract: A gate-coupled MOSFET ESD protection circuit. The circuit has a gate-node potential controlled by an inverter and a timing control circuit. Unlike current-shunting ESD clamping devices that turn the MOSFET fully on during an ESD event, a pull-down element is included to form a voltage divider like circuit, such that the gate-node potential is limited to around 1 to 2 volts during a positive ESD transient event. Unlike GCNMOS (Gate-Coupled NMOS), the invention has better control of the transient gate potential for more effective triggering of the NMOS into snapback during an ESD event.

Abstract: An electrostatic discharge protection device formed on a substrate. The electrostatic discharge protection device includes a first isolation region formed over the substrate, an active region formed over the substrate and enclosed by the first isolation region, a second isolation region formed on the substrate and substantially surrounded by the active region, a first gate element formed in the active region, the first gate element having a first end extending over the first isolation region and a second end extending over the second isolation region, a drain region formed in the active region at a first side of the first gate element, a source region formed in the active region at a second side of the first gate element, a drain contact for electrically coupling the drain region to a first node, and a source contact for electrically coupling the source region to a second node.

Abstract: For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

Abstract: ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: A number of different arrangements of island structures are utilized for improved ESD protection. The MOSFET structure provides islands that are selectively positioned among a group of ESD protection devices for protecting the power-bus, input pins, output pins and I/O pins to achieve ESD improvement in a manner which improves overall ESD protection strength while reducing the complexity of IC simulation and modeling.

Abstract: A method of operating a non-volatile memory device includes providing the non-volatile memory device with a body of first conductivity, a source region of second conductivity, a drain region of second conductivity on the body, and a control gate over the body adjacent to the source and drain regions. A first voltage of first polarity is applied to the control gate. A second voltage of first polarity is applied to the drain region, the second voltage being less than about 5.6 volts. A third voltage of second polarity is applied to the source region.

Abstract: A pin-assignment method is provided for use on an IC package to arrange pin connections. The pin-assignment method can allow an improvement in the electro-static discharge (ESD) protection capability for the IC chip packed in the IC package. Specifically, the pin-assignment method organizes the no-connect pins of the IC package into groups and then assigns each of the two pins that bound each no-connect pin group to be connected to a power bus of the IC chip. This allows for an increased ESD protective capability for the no-connect pins. Moreover, the pin-assignment method can simplify the wiring complexity of the IC package.

Abstract: ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: The present invention provides a buffer for voltage ringing and overshooting suppression that improves the ESD protection. The buffer comprises a transistor and a resistance modulator. The resistance modulator is connected in series between an IC pad and a power node. The resistance modulator provides a first resistance during normal circuit operation, and provides a second resistance that is lower than the first resistance during an ESD event.

Abstract: A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. A guard band structure is formed in a spaced apart relationship from the metal bond pad layer which is connected to the underlying layer by a hole-fill. The underlying layer can be a metal layer, a semiconductor layer such as a polysilicon layer, or any material layer which has good adhesion with the hole fill material. The guard band structure exerts a downward force against the middle dielectric layer to help keeping the middle dielectric layer in place.

Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: A high-voltage tolerance input buffer and a high-voltage ESD protection circuit connected to a pad of an integrated circuit for preventing rapid gate oxide aging. The high-voltage tolerance input buffer of the present invention comprises a voltage-sharing circuit and a switch circuit, wherein the voltage-sharing circuit is connected between the pad and a power rail and generates a reference voltage not higher than the voltage of the pad. The switch circuit is connected to the voltage-sharing circuit and comprises a control gate to control the switching operation of the switch circuit according to the reference voltage. The present invention can be implemented to solve the rapid gate oxide aging problem without incurring any change in the original process flow by employing a voltage-sharing circuit.

Abstract: A number of different arrangements of island structures are utilized for improved ESD protection. The MOSFET structure provides islands that are selectively positioned among a group of ESD protection devices for protecting the power-bus, input pins, output pins and I/O pins to achieve ESD improvement in a manner which improves overall ESD protection strength while reducing the complexity of IC simulation and modeling.

Abstract: The present invention is directed to a semiconductor integrated circuit device having reduced leakage and the method of operating a semiconductor integrated circuit device with reduced leakage. The invention comprises an integrated circuit, including a passing transistor and a bias-application device coupled to the substrate of the passing transistor. The present invention has the passing transistor coupled to a storage cell. The bias-application device applies a first bias voltage of a positive value when the passing transistor is inactivated and applies a second bias voltage when the passing transistor is activated, wherein the second bias voltage is equal to or smaller than the first bias voltage. Further in accordance with the invention, there is provided a method of reducing the leakage of a passing transistor of N-type. The passing transistor is coupled with a storage cell.