Abstract: A driving circuit suitable for driving pixels in an LCD array includes dual channel digital-to-analog converters (DACs). Each dual channel DAC outputs on channel A and channel B outputs the analog version of an applied digital signal and a non-passing voltage, respectively, and switches these outputs in response to a toggle signal. The DAC outputs are applied to paired output transistors such that one transistor of each transistor pair is rendered conductive and the other transistor is rendered non-conductive during each display cycle. By designating alternate DACs to receive upper and lower voltage range driving voltages, respectively, each pixel is alternately driven by voltages in the upper and lower voltage range and the driving voltage range applied to each pixel in one display cycle is opposite to the voltage range applied to the immediately adjacent pixels in the same display cycle.

Abstract: The present invention provides a buffer for voltage ringing and overshooting suppression that improves the ESD protection. The buffer comprises a transistor and a resistance modulator. The resistance modulator is connected in series between an IC pad and a power node. The resistance modulator provides a first resistance during normal circuit operation, and provides a second resistance that is lower than the first resistance during an ESD event.

Abstract: A bond pad structure for use in wire bonding applications during the packaging of semiconductor devices with reduced bond pad lift-off problem. The bond pad structure contains: (a) a metal bond pad formed in an open window area surrounded by an edge portion of a dielectric layer; and (b) at least one dendritic sub-structure formed in the edge portion of the dielectric layer. The at least one dendritic sub-structure is formed of a metal material and is in contact with the metal bond pad. The dendritic sub-structure is a generally cross-shaped structure containing a first segment which is generally perpendicular to an edge of the metal bond pad to which the dendritic sub-structure is connected, and a second segment with is generally parallel to the edge. The dendritic sub-structure serves two main purposes.

Abstract: The output buffer of the present invention comprises a pull up circuit and a pull down circuit. The pull up circuit is coupled between a first power line and a pad. The pull down circuit coupled between a second power line and the pad is comprised of a resistor, a diode and an electrostatic discharge protection component. The resistor deposited on the substrate of a first conductivity type is comprised of a well region of a second conductivity type and has a first end and a second end. The first end is a forth doped region of the second conductivity type and coupled to the pad. The diode is formed in the well region, construct by the PN junction formed between a first doped region of the first conductivity type and the well region. The electrostatic discharge component is coupled between the second end and the second power line. The first doped region is electrically floated in the well regions.

Abstract: A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a top dielectric layer, a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. The bond frame structure, which is formed in a spaced apart relationship from the metal bond pad layer contains a plurality of island elements formed on top of the middle dielectric layer and an interconnected frame element formed on top of the top dielectric layer. The frame element contains a portion which overlaps with a portion of the metal bond pad layer, so as to exert a downward force to prevent the metal bond pad layer from peeling off.

Abstract: A method of processing memory, suitable for loading an executable object code compiled from a source code into the memory that includes defective memory cells. At first, set up a plurality of pre-compiled object codes that correspond to a source code, each pre-compiled object code having at least a skipped-code-address range. Then, test the memory and locate the defective addresses therein. According to the result of the test, the code-loading system selects an executable object that has the matching skipped-code-address range from the pre-compiled object codes, and loads the executable code into the memory. Since the skipped-code-address range covers the defective addresses in the memory, the defective memory cells in the memory won't affect the operation of loading a program.

Abstract: A transient negative voltage pump circuit pumps the ESD voltage to a negative voltage. The negative voltage with the ESD voltage are used for early triggering of an SCR structure on the integrated circuit. In one version of the present invention, a pn junction diode of the SCR device is used as part of the negative voltage pump circuit. This saves the layout area while improving the ESD performance. The present invention improves the ESD performance of an SCR ESD protection circuit which is used for protecting the power bus or an IC pin during an ESD event.

Abstract: For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing through the critical-path, to save power when not boosting speed.

Abstract: A bond pad structure for use in wire bonding applications during the packaging of semiconductor devices which minimizes the bond pad lift-off problem to provide improved stability. The bond pad structure contains: (1) a dielectric layer 4 formed on a first conductive layer 5; (2) a base conductive layer (whose outer boundary as viewed from the top is indicated as line 11) formed in the dielectric layer on top of the first conductive layer, the base conductive being extended to form an overhang layer (whose outer boundary is shown as line 13) which is disposed above the dielectric layer; and (3) at least one recessed portion 20 formed in the overhang layer. In a preferred embodiment, the bond pad is rectangular in shape and the recessed portion has the shape of an elongated rim that covers two corners of the base conductive layer.

Abstract: For low-voltage and high-speed operation of a MOSFET in an integrated circuit, a small voltage is applied to a source node, causing slight forward bias of the source junction and thereby reducing its threshold voltage. Due to the combined effects of the bias at the source node and a body effect, the reduction in threshold voltage is larger than the absolute value of the source voltage being applied. A performance improvement over simply applying a bias voltage to the body (well) results. Detection of an event can be used to apply the performance boost to a critical path in the integrated circuit only when needed. Upon detection of a logic event, which determines that a signal will propagate through the critical path shortly thereafter, the source-node bias for circuit elements in the critical path can be adjusted in time for a speed improvement. However, the source remains at another potential when no signal is passing| through the critical-path, to save power when not boosting speed.

Abstract: An IC package architecture with electrostatic discharge (ESD) protection is provided for use on an IC package for the purpose of allowing the ESD robustness of the IC package to be further enhanced and the structural complexity of the same to be further simplified as compared to the prior art. The IC package includes a lead frame having a die pad for mounting an IC chip thereon, a plurality of package pins with some no-connect pins which are grouped into at least one no-connect pin unit, each unit consisting, of one single no-connect pin or a number of consecutively arranged no-connect pins.

Abstract: An ESD protective device for protection of an integrated circuit (IC) package from electrostatic discharge damage. The ESD protective device protects the internal circuit of the IC connected to wired pins of the IC package against ESD damage due to ESD stress in neighboring no-connect pins. The ESD protective device includes an ESD protective unit coupled to the power bus and a bonding pad coupled between this ESD protective device and the no-connect pin. The ESD protective unit causes ESD stress applied to the no-connect pin to be diverted to the power bus, thus preventing ESD transfer between a no-connect pin and an active pin, which could damage the internal circuit.

Abstract: An IC package architecture with electrostatic discharge (ESD) protection is provided for use on an IC package for the purpose of allowing the ESD robustness of the IC package to be further enhanced and the structural complexity of the same to be further simplified as compared to the prior art. The IC package includes a lead frame having a die pad for mounting an IC chip thereon, a plurality of package pins with some no-connect pins which are grouped into at least one no-connect pin unit, each unit consisting of one single no-connect pin or a number of consecutively arranged no-connect pins.

Abstract: A method is provided for use on a parametric tester that allows the parametric tester to more effectively and precisely measure the output frequency of a periodic pulse signal generating means. The first step is to down convert the output frequency of the periodic pulse signal generating means to about 1 Hz. Then, the frequency-downconverted pulse train is sampled to thereby obtain a series of sampled signals In accordance with the magnitudes of the sampled signals, the sampled signals are registered to be at either a high-level state, an low-level state, or a intermediate-level state. Then, the integration time and the delay time involved in the sampling process are registered. The sampling process is continued until at least two sampled signals at the low-level state are registered. Based on these parameters, a delta transition time for the first intermediate-level state and a second delta transition time for the second intermediate-level state can be obtained.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: A transient voltage-pump circuit pumps the ESD voltage to a higher voltage. The pumped-high transient voltage is used for early triggering of an SCR. In one version of the present invention, a pn junction of the SCR device is used as part of the voltage-pump circuit. This saves the layout area while improving the ESD performance. The present invention improves the ESD performance of an SCR ESD protection circuit which is used for protecting the power bus or an IC pin during an ESD event.

Abstract: A bond pad structure for use in wire bonding applications during the packaging of semiconductor devices with reduced bond pad lift-off problem. It includes: (a) a laminated structure containing a metal bond pad layer, a dielectric layer, and an underlying layer formed on a wafer surface; and (b) a single anchoring structure formed in said dielectric layer connecting said metal bond pad layer and said underlying layer. The single anchoring structure contains a plurality of line segments that are interconnected so as to form said single anchoring structure. Unlike prior art anchoring structures, which always contain a plurality of anchors buried inside the dielectric, the bond pad structure contains only a single anchoring structure, which can have the geometry of an open or closed ring with whiskers, a coil, an open or closed square-waved ring, a tree structure, a grid-line structure, a meandering structure, a serpentine structure, a spiral structure, or a labyrinth.

Abstract: A memory writer has the capability to modify the machine code according to the defective memory-cell locations, such that the modified code functionally bypasses all defective memory-cell addresses upon program execution. The machine code is modified without re-compilation of the microprogram, instead, it is modified by inserting jump machine-code instructions directly between instruction steps, and to insert dummy bytes between adjacent memory space allocations for symbols definition. The machine code is further modified to take into account of the effect of the insertion of additional codes on the instruction within the machine code that involve the address referencing. The modified machine code, when written to the partially defective memory, performs identical routines while bypassing all defective memory-cell addresses. The present invention is useful for writing a microprogram in non-volatile memories, such as EPROM, EEPROM or Flash/EEPROM.

Abstract: In a multiple-supply CMOS IC, if VDDH is applied slower than VDDL during powering up, some diffusion junctions normally reversed-biased may momentarily become forward-biased and produce latch-up to produce permanent damage to circuits. Therefore a protection circuit against latch-up in a multiple-supply IC is provided. The protection circuit comprises an N-channel MOSFET, which has its gate connected to the high-voltage bus, its drain connected to the low-voltage supply, and its source connected to the low-voltage bus to control the power-up sequence of high voltage and low voltage for the multiple-supply IC and to prevent latch-up. The N-channel MOSFET can be of different modes, such as enhancement mode, depletion mode or enhancement mode having a low threshold voltage.