Abstract: A multi-gate-finger MOSFET structure positions the gate element over a channel between drain and source diffusion regions, such that the entire structure is within the active region in a substrate. The gate/channel-to-drain and gate/channel-to-source diffusion edges are effectively continuous along the gate/channel layout, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. In addition, multiple poly-gate extensions are incorporated to reduce the gate resistance, thereby minimizing the propagation delay of the gate signal.

Abstract: ESD protection devices and methods to form them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process, ESD protection devices with a lower trigger voltage are provided. The NMOS for ESD protection according to the present invention has islands with thin gate oxides and a control gate with a thick gate oxide. These islands overlap the drain region of the NMOS to reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.

Abstract: The present invention is directed to a semiconductor integrated circuit device having reduced leakage and the method of operating a semiconductor integrated circuit device with reduced leakage. The invention comprises an integrated circuit, including a passing transistor and a bias-application device coupled to the substrate of the passing transistor. The present invention has the passing transistor coupled to a storage cell. The bias-application device applies a first bias voltage of a positive value when the passing transistor is inactivated and applies a second bias voltage when the passing transistor is activated, wherein the second bias voltage is equal to or smaller than the first bias voltage. Further in accordance with the invention, there is provided a method of reducing the leakage of a passing transistor of N-type. The passing transistor is coupled with a storage cell.

Abstract: An IC package architecture with electrostatic discharge (ESD) protection is provided for use on an IC package for the purpose of allowing the ESD robustness of the IC package to be farther enhanced and the structural complexity of the same to be further simplified as compared to the prior art. The IC package includes a lead frame having a die pad for mounting an IC chip thereon, a plurality of package pins with some no-connect pins which are grouped into at least one no-connect pin unit, each unit consisting of one single no-connect pin or a number or consecutively arranged no-connect pins.

Abstract: The present invention provides an ESD protection device with isolated islands and an n well. At least one of the isolated islands has an end apart from the boundary of a drain diffusion region of the ESD protection device, to form a gap between. The n well overlaps with the isolated islands and is kept at least a designated distance away from a channel region of the ESD protection device. An interlocked structure of isolated islands is also provided in this invention to direct ESD current flowing forward and backward to the channel region of the ESD protection device, thereby increasing the distributed resistance of the drain diffusion region. Several benefits, such as lower drain capacitance, lower standby power consumption and a wider range of adjustable resistance, are achieved.

Abstract: A semiconductor device has a first diffusion region having a silicided portion and a non-silicided portion. The device also has a second diffusion region, and a channel region between the first and second diffusion regions. The non-silicided portion of the first diffusion region has a plurality of non-silicided regions.

Abstract: A latch-up protection circuit for an integrated circuit powered through a first power rail and a second power rail is disclosed, the integrated circuit having at least one semiconductor bulk of a conductivity type. The latch-up protection circuit comprises a control circuit and a switch circuit. The control circuit is connected to the first power rail and the second power rail for detecting a relative voltage therebetween and generating a first control signal and a second control signal. The switch circuit connected to the first power rail and the control circuit. When the relative voltage is greater than a first predetermined value, the switch circuit in response to the first control signal electrically connects the first power rail with the at least one semiconductor bulk. When the relative voltage is smaller than the first predetermined value, the switch in response to the first control signal electrically disconnects the first power rail from the at least one semiconductor bulk.

Abstract: A bond pad structure for use in wire bonding application during the packaging operation of semiconductor devices which contains a bond frame structure for holding the bond pad in place to prevent bond pad peel-off problem. The bond pad structure is a laminated structure containing a metal bond pad layer, a middle dielectric layer, and an underlying layer formed above a wafer surface. A guard band structure is formed in a spaced apart relationship from the metal bond pad layer which is connected to the underlying layer by a hole-fill. The underlying layer can be a metal layer, a semiconductor layer such as a polysilicon layer, or any material layer which has good adhesion with the hole fill material. The guard band structure exerts a downward force against the middle dielectric layer to help keeping the middle dielectric layer in place.

Abstract: A driver circuit for use in driving displays has an input receiving a digital input data having n bits for selecting one of a plurality of voltage levels for driving the circuit. The circuit also has an output, a plurality of digital signal lines coupled to the digital input data, and a plurality of active regions coupled to a first side of the output. Each of the plurality of active regions is coupled to a separate voltage level. The circuit further includes a plurality of pass transistors at a first subset of locations where the plurality of digital signal lines overlap the plurality of active regions, and a plurality of depletion-implanted transistors at a second subset of locations where the plurality of digital signal lines overlap the plurality of active regions. The number of the plurality of digital signal lines on one side of the output can be odd number, such as 2n−1, or can be 2n−2.

Abstract: A method of operating a flash memory structure including a programming step. The method includes providing a flash memory device, the flash memory device comprising a substrate of first conductivity type, a source region of second conductivity type being defined in the substrate and a drain region of second conductivity type defined in the substrate. The flash memory device can be a split gate, a stacked gate, or other type of physical structure. The method includes applying a drain voltage of first polarity type on the drain region and applying a control gate voltage of a first conductivity type on the control gate. The method also includes applying a source voltage of second polarity type ranging from about 0.1 volt to about 0.5 volt on the source region, while maintaining a ground potential on the substrate to inject electrons onto a floating gate to program the floating gate.

Abstract: An integrated semiconductor device includes a substrate having a buried shallow trench isolation structure and an epitaxial layer disposed over the substrate and the buried shallow trench isolation structure. The epitaxial layer includes a shallow trench isolation structure that extends over the buried shallow trench isolation structure in the substrate to substantially reduce leakage current in the substrate to prevent device latch-up.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. A plurality of current divider segments are distributed on the drain region and extend between the gate and drain contacts. The segments can be formed of polysilicon or a field oxide.

Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. One or more islands are distributed either symmetrically or non-symmetrically in and along the drain region. The islands can be formed of polysilicon or a field oxide.

Abstract: The present invention provides a low-voltage-triggered electrostatic discharge (LVTESD) protection circuit coupled to a pad of an integrated circuit (IC) to protect core circuits of the IC from ESD. The ESD protection circuit comprises a semiconductor substrate having the first conductivity type, a well region having the second conductivity type is formed in the semiconductor substrate, and an anode-doped region having the first conductivity type and formed in the well region to become an anode of a semiconductor control rectifier (SCR). A gate structure is formed in the semiconductor substrate outside the well region. A first doped region having the second conductivity type is formed between the well region and the gate structure in the semiconductor substrate. A second doped region having the second conductivity type is formed adjacent to the second side of the gate structure in the semiconductor substrate.

Abstract: A MOSFET structure uses angled poly-gate segments positioned between drain and source diffusion regions such that the entire continuous gate element structure is within the active region in a substrate. The gate-to-source diffusion edges are continuous along the gate body, so as to cascade the snap-back action to enhance uniform turn on of the entire gate element during an ESD event. The angled gate segments provide a total gate-to-area ratio greater than that of a multi-finger-gate configuration within an equal size active region. In addition, the gate signal RC delay is sufficient to provide noise suppression of the output voltage when the MOSFET is used as a high current-drive CMOS output buffer.

Abstract: A method for transmitting image data of a scanner is disclosed, in which the transmitted image data is divided into two portions, i.e., the uncompressed portion of low-resolution data and the compressed portion of the data difference. The compressed portion of the data difference can be decompressed and then combined with the uncompressed portion of low-resolution data to obtain an image in a high resolution. Thus the scanned image in a low resolution, a medium resolution or a high resolution can be optionally displayed. While displaying the scanned image, the low-resolution image can be first displayed. If the low-resolution image is acceptable, the compressed-data difference values do not need to be processed and can be directly disregarded. Therefore, the data to be transmitted and processed during the scanning process can be reduced to accelerate the scanning and displaying speed.

Abstract: A latch-up protection circuit is integrated with a CMOS circuitry, which is powered by a first voltage and a second voltage via a first power rail and a second power rail, respectively, on a semiconductor substrate. The latch-up protection circuit of the present invention comprises: a well of a first conductivity type, a first diffusion region of the first conductivity type, a second diffusion region of a second conductivity type, and a third diffusion region of the second conductivity type. The well is formed in the semiconductor substrate to establish a junction therebetween. The first diffusion region is formed in the well and connected to the first power rail. The second diffusion region is formed in the well and connected to the second power rail, where the second diffusion region is spaced from the junction by a first spacing.

Abstract: A computer system is provided that loads a computer program, in a reverse order, into a memory device having one or more defective memory cells. The program is organized into code modules with each code module including at least one complete instruction, or data block. The last code module of the program is loaded first into the last or highest addresses of the address space allocated in the memory for the program. Thereafter, the code module preceding the last loaded code module of the program is loaded into the addresses preceding the previously-loaded addresses. The subsequent code modules are loaded into successively lower memory addresses in a reverse fashion until the first code module of the program is loaded into memory. As each code module, or the codes that make up the code module, are loaded, each loaded memory address is checked for a defective cell.

Abstract: A method of operating a flash memory structure including a programming step. The method includes providing a flash memory device, the flash memory device comprising a substrate of first conductivity type, a source region of second conductivity type being defined in the substrate and a drain region of second conductivity type defined in the substrate. The flash memory device can be a split gate, a stacked gate, or other type of physical structure. The method includes applying a drain voltage of first polarity type on the drain region and applying a control gate voltage of a first conductivity type on the control gate. The method also includes applying a source voltage of second polarity type ranging from about 0.1 volt to about 0.5 volt on the source region, while maintaining a ground potential on the substrate to inject electrons onto a floating gate to program the floating gate.

Abstract: A driving circuit such as for driving pixels of an LCD includes first and second digital-to-analog converters respectively coupled to receive first and second digital input values. The outputs of the first and second digital-to-analog converters are connected to first and second output transistors, the outputs of which are connected together to a driving voltage output terminal. A predetermined voltage is applied to the gate of each output transistor. The first and second digital-to-analog converters and their associated output transistors correspond to upper and lower ranges of output voltage. During a display cycle, one digital-to-analog converter receives a digital value to be output as a driving voltage, while the other digital-to-analog converter receives a digital value to be output as a voltage that renders its associated output transistor nonconductive.