Patents by Inventor Shian-Jyh Lin

Shian-Jyh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9779957
    Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: October 3, 2017
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Shian-Jyh Lin, Jeng-Ping Lin, Chin-Piao Chang, Jen-Jui Huang
  • Patent number: 9214571
    Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: December 15, 2015
    Assignee: NANYA TECHNOLOGY CORP.
    Inventor: Shian-Jyh Lin
  • Publication number: 20150179822
    Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
    Type: Application
    Filed: March 9, 2015
    Publication date: June 25, 2015
    Inventor: Shian-Jyh Lin
  • Patent number: 9024377
    Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: May 5, 2015
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Publication number: 20140342567
    Abstract: A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.
    Type: Application
    Filed: July 31, 2014
    Publication date: November 20, 2014
    Inventors: Shian-Jyh Lin, Jeng-Ping Lin, Chin-Piao Chang, Jen-Jui Huang
  • Patent number: 8691705
    Abstract: A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: April 8, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Chih-Wei Huang, Chao-Sung Lai, Hsing-Kan Peng, Chung-Yuan Lee, Shian-Jyh Lin
  • Publication number: 20140070359
    Abstract: A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Inventors: Shian-Jyh Lin, Jeng-Ping Lin, Chin-Piao Chang, Jen-Jui Huang
  • Publication number: 20140036565
    Abstract: An exemplary memory device includes a substrate and two word lines extending on the substrate. The substrate includes an active area. The two word lines are formed on the active area. Each word line includes a recessed portion corresponding to the active area. The recessed portion is defined by a planar top surface.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: Nanya Technology Corporation
    Inventors: Shian Jyh LIN, Jen Jui Huang
  • Publication number: 20130302968
    Abstract: A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area that comprises source and drain regions. The first and second trench isolations extend parallel to each other. The plurality of line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area. The first word line is formed in the substrate and adjacent to the first trench isolation. The first word line defines a first segment of the active area with the first trench isolation. The second word line extends across the active area. The second word line is formed in the substrate and adjacent to the second trench isolation. The second word line defines a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 14, 2013
    Inventors: SHIAN JYH LIN, JEN JUI HUANG
  • Publication number: 20130299884
    Abstract: A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area having source and drain regions. The first and second trench isolations extend parallel to each other. The line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area and is formed in the substrate adjacent to the first trench isolation defining a first segment of the active area with the first trench isolation. The second word line extends across the active area and is formed in the substrate adjacent to the second trench isolation defining a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 14, 2013
    Applicant: Nanya Technology Corporation
    Inventors: Shian Jyh Lin, Jen Jui Huang
  • Publication number: 20130153982
    Abstract: A semiconductor device capable of reducing influences of adjacent word lines is provided in the present invention. The semiconductor device includes: a substrate, and a word line disposed in the substrate. The word line includes: a gate electrode, a gate dielectric layer disposed between the gate electrode and the substrate and at least one first charge trapping dielectric layer disposed adjacent to the gate electrode, wherein the first charge trapping dielectric layer comprises HfO2, TiO2, ZrO2, a germanium nanocrystal layer, an organic charge trapping material, HfSiOxNy, or MoSiOqNz.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventor: Shian-Jyh Lin
  • Patent number: 8202801
    Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: June 19, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Publication number: 20120142187
    Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
    Type: Application
    Filed: February 21, 2012
    Publication date: June 7, 2012
    Inventor: Shian-Jyh Lin
  • Patent number: 8148824
    Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: April 3, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Patent number: 8143121
    Abstract: A transistor structure includes a semiconductor substrate having a top surface and sidewalls extending downward from the top surface, wherein each of the sidewall comprises a vertical upper sidewall surface and a lower sidewall recess laterally etched into the semiconductor substrate. A trench fill dielectric region is inlaid into the top surface of the semiconductor substrate. Two source/drain regions are formed into the top surface of the semiconductor substrate and are sandwiched about the trench fill region. A buried gate electrode is embedded in the lower sidewall recess. A gate dielectric layer is formed on surface of the lower sidewall recess between the semiconductor substrate and the buried gate electrode.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: March 27, 2012
    Assignee: Nanya Technology Corp.
    Inventor: Shian-Jyh Lin
  • Publication number: 20110260297
    Abstract: A method for fabricating a through-substrate via structure. A semiconductor substrate is provided. A first via hole is etched into the semiconductor substrate. A spacer is formed on sidewall of the first via hole. The semiconductor substrate is etched through the first via hole to form a second via hole. The second via hole is wet etched to form a bottle-shaped via hole. An insulating layer is formed lining a lower portion of the bottle-shaped via hole. A first conductive layer is deposited within the bottle-shaped via hole, wherein the first conductive layer define a cavity. A bond pad is formed on a front side of the semiconductor substrate, wherein the bond pad is electrically connected with the first conductive layer. A back side of the semiconductor substrate is polished to reveal the cavity. The cavity is filled with a second conductive layer.
    Type: Application
    Filed: April 27, 2010
    Publication date: October 27, 2011
    Inventors: Shian-Jyh Lin, Shing-Hwa Renn
  • Patent number: 8044449
    Abstract: A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: October 25, 2011
    Assignee: Nanya Technology Corporation
    Inventors: Shian-Jyh Lin, Hung-Chang Liao, Meng-Hung Chen, Chung-Yuan Lee, Pei-Ing Lee
  • Publication number: 20110254169
    Abstract: A through substrate via having a low stress is provided. The through substrate via is positioned in a substrate. The through substrate via includes: an outer tube penetrating the substrate; at least one inner tube disposed within the outer tube; a dielectric layer lining on a side wall of the outer tube, and a side wall of the inner tube; a strength-enhanced material filling the inner tube; and a conductive layer filling the outer tube.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 20, 2011
    Inventor: Shian-Jyh Lin
  • Publication number: 20110226736
    Abstract: A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed.
    Type: Application
    Filed: May 31, 2011
    Publication date: September 22, 2011
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih-Wei Huang, Chao-Sung Lai, Hsing-Kan Peng, Chung-Yuan Lee, Shian-Jyh Lin
  • Patent number: 7985998
    Abstract: A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: July 26, 2011
    Assignee: Nanya Technology Corp.
    Inventors: Shian-Jyh Lin, Ming-Cheng Chang, Neng Tai Shih, Hung-Chang Liao