Abstract: An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.

Abstract: A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period.

Abstract: An integrated circuit including a plurality of sensors configured to sense variations in supply voltage levels at points within the integrated circuit is disclosed. The plurality of sensors are distributed across the integrated circuit and have transistor devices such that process variations in the transistor devices within the sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying within a pre-defined voltage offset range. The integrated circuit is configured to transmit results from multiple ones of the plurality of sensors to processing circuitry such that the variations in the supply voltage levels can be determined with a voltage offset range that is reduced compared to the pre-defined voltage offset range.

Abstract: An integrated circuit includes processing pipeline circuitry comprising a plurality of pipeline stages separated by respective signal value storage circuitry. Timing detection circuitry to the processing pipeline circuitry serves to detect as timing violations any signal transitions arrive at the signal value storage circuits outside respective nominal timing windows. Error detection circuitry triggers an error correcting response if the timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over a plurality of clock cycles of a clock signal controlling the processing pipeline circuitry. The predetermined pattern may be two consecutive timing violations.

Abstract: A circuit delay monitoring apparatus has a ring oscillator with a plurality of delay elements, a signal transition being propagated through the delay elements of the ring oscillator, and a plurality N of sampling points being distributed around the ring oscillator. Selection circuitry selects, in dependence on the indication of the current location of the signal transition generated by the fine sampling circuitry, one of the M transition counter circuits whose associated location is greater than said predetermined amount from the current location of the signal transition. Output generation circuitry then generates a count indication for a reference time period dependent on a sampled count value of the transition counter circuit selected by the selection circuitry, the indication of the current location of the signal transition within the ring oscillator, and reference count data relating to the start of the reference time period.

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract: A data processing system 2 is used to perform processing operations to generate a result value. The processing circuitry which generates the result value has an error resistant portion 32 and an error prone portion 30. The probability of an error in operation of the error prone portion for a given set of operating parameters (clk, V) is greater than the probability of an error for that same set of operating parameters within the error resistant portion. Error detection circuitry 38 detects any errors arising in the error prone portion. Parameter control circuitry 40 responds to detected errors to adjust the set of operating parameters to maintain a non-zero error rate in the errors detected by the error detection circuitry. Errors within the one or more bits generated by the error prone portion are not corrected as the apparatus is tolerant to errors occurring within such bit values of the result value.

Abstract: A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry.

Abstract: An integrated circuit 114 includes processing pipeline circuitry 40 comprising a plurality of pipeline stages 44, 46, 48 separated by respective signal value storage circuitry 48, 50, 52. Timing detection circuitry 54, 56, 58 coupled to the processing pipeline circuitry serves to detect as timing violations any signal transitions arrive at the signal value storage circuits outside respective nominal timing windows. Error detection circuitry 66 triggers an error correcting response if the timing detection circuitry indicates a predetermined pattern comprising a plurality of timing violations spread over a plurality of clock cycles of a clock signal CK controlling the processing pipeline circuitry. The predetermined pattern may be two consecutive timing violations.

Abstract: An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.

Abstract: An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus and includes a sequential storage structure arranged to latch an output signal generated by combinatorial circuitry dependent on a second clock signal. The sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry. The sequential storage structure can be operated in either first or second modes of operation where, in the first mode, the predetermined timing window is ahead of a time at which the main storage element latches said value of the output signal enabling an approaching setup timing error to be detected. In the second mode, the predetermined timing window is after the time at which the main storage element latches said value of the output signal where an approaching hold timing error is detected.

Abstract: A D-type flip-flop includes tristate inverter circuitry passing a processing signal through to storage circuitry 8 from where the processing signal passes via a transmission gate to slave storage circuitry. A transition detector is coupled to the input node of the storage circuitry and serves to generate an error signal if a transition is detected upon that input node during an error detecting period. Other forms of this technique may provide clock gating circuitry.

Abstract: An integrated circuit comprising a plurality of sensors configured to sense variations in supply voltage levels at points within the integrated circuit is disclosed. The plurality of sensors are distributed across the integrated circuit and have transistor devices such that process variations in the transistor devices within the sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying within a pre-defined voltage offset range. The integrated circuit is configured to transmit results from multiple ones of the plurality of sensors to processing circuitry such that the variations in the supply voltage levels can be determined with a voltage offset range that is reduced compared to the pre-defined voltage offset range.

Abstract: Signal value storage circuitry 2 includes transparent storage circuitry 4, transition detector circuitry 6 and error detecting circuitry 8. The transition detector circuitry serves to generate a detection pulse when a signal transition is detected at a signal node NS within the transparent storage circuitry. The error detecting circuitry generates an error indicating signal when this detection pulse overlaps in time with the non-transparent phase of a pulse clock signal controlling the signal valve storage circuitry for at least an overlap period TOV.

Abstract: A D-type flip-flop 2 includes tristate inverter circuitry 4, 6 passing a processing signal through to storage circuitry 8 from where the processing signal passes via a transmission gate 10 to slave storage circuitry 12. A transition detector 16 is coupled to the input node nm of the storage circuitry 8 and serves to generate an error signal if a transition is detected upon that input node during an error detecting period. Other forms of this technique may provide clock gating circuitry.

Abstract: A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.