Patents by Inventor Shigemasa Shiota
Shigemasa Shiota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8897736Abstract: A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Specifically, the following is implemented: when there is the supply of required power from the battery, it is made possible to carry out high-performance, multifunctional authentication and settlement processing making good use of high-speed processing, mass storage, and the like which are the advantages of the security controller essentially driven by battery; and in an anomalous instance in which the battery remaining capacity is lost, it is made possible to carry out minimal authentication and settlement processing.Type: GrantFiled: June 19, 2013Date of Patent: November 25, 2014Assignee: Renesas Electronics CorporationInventors: Shigemasa Shiota, Kunihiro Katayama, Shinichi Fukasawa, Takeo Kon, Seiji Kobayashi
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Publication number: 20140289538Abstract: A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.Type: ApplicationFiled: June 3, 2014Publication date: September 25, 2014Applicant: Renesas Electronics CorporationInventors: Daisuke OSHIDA, Masayuki HIROKAWA, Akira YAMAZAKI, Takashi FUJIMORI, Shigemasa SHIOTA, Shigeru FURUTA
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Patent number: 8782432Abstract: A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.Type: GrantFiled: June 15, 2012Date of Patent: July 15, 2014Assignee: Renesas Electronics CorporationInventors: Daisuke Oshida, Masayuki Hirokawa, Akira Yamazaki, Takashi Fujimori, Shigemasa Shiota, Shigeru Furuta
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Publication number: 20140185380Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: August 6, 2013Publication date: July 3, 2014Applicant: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi INOUE, Shigemasa SHIOTA, Masashi NAITO
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Publication number: 20140133652Abstract: In a semiconductor device and an information processing system according to one embodiment, an external device generates external device unique information by using a unique code which is a value unique to the semiconductor device, and generates second information by encrypting the first information with the use of the external device unique information. The semiconductor device stores the second information and generates the principal device unique information independently of the external device, with the use of the unique code of the semiconductor device holding the second information, and decrypts the second information with the use of the principal device unique information to obtain the first information.Type: ApplicationFiled: October 28, 2013Publication date: May 15, 2014Applicant: Renesas Electronics CorporationInventors: Daisuke OSHIDA, Shigemasa SHIOTA
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Publication number: 20140011451Abstract: A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Specifically, the following is implemented: when there is the supply of required power from the battery, it is made possible to carry out high-performance, multifunctional authentication and settlement processing making good use of high-speed processing, mass storage, and the like which are the advantages of the security controller essentially driven by battery; and in an anomalous instance in which the battery remaining capacity is lost, it is made possible to carry out minimal authentication and settlement processing.Type: ApplicationFiled: June 19, 2013Publication date: January 9, 2014Applicant: Renesas Electronics CorporationInventors: Shigemasa Shiota, Kunihiro Katayama, Shinichi Fukasawa, Takeo Kon, Seiji Kobayashi
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Patent number: 8503235Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: November 17, 2011Date of Patent: August 6, 2013Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 8478224Abstract: A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Thus the noncontact authentication and settlement functions can be used even after the battery remaining capacity is lost by use of a communication function for the principal purpose.Type: GrantFiled: July 18, 2010Date of Patent: July 2, 2013Assignee: Renesas Electronics CorporationInventors: Shigemasa Shiota, Kunihiro Katayama, Shinichi Fukasawa, Takeo Kon, Seiji Kobayashi
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Publication number: 20120324310Abstract: A semiconductor device in related art has a problem that security at the time of writing data cannot be sufficiently assured. A semiconductor device of the present invention has: a unique code generating unit generating an initial unique code which is a value unique to a device and includes an error in a random bit; a first error correcting unit correcting an error in the initial unique code to generate an intermediate unique code; a second error correcting unit correcting an error in the intermediate unique code to generate a first determinate unique code; and a decrypting unit decrypting, with the first determinate unique code, transmission data obtained by encrypting confidential information with key information generated on the basis of the intermediate unique code by an external device to generate confidential information.Type: ApplicationFiled: June 15, 2012Publication date: December 20, 2012Inventors: Daisuke OSHIDA, Shigeru Furuta, Masayuki Hirokawa, Akira Yamazaki, Takashi Fujimori, Shigemasa Shiota
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Publication number: 20120324241Abstract: A semiconductor device in related art has a problem that security on confidential information stored is insufficient. A semiconductor device of the present invention has a unique code which is unique to a device and generates unique code corresponding information from the unique code. The semiconductor device has a memory region in which specific information obtained by encrypting confidential information is stored in a region associated with the unique code corresponding information. The specific information read from the memory region is encrypted with the unique code corresponding information to generate the confidential information.Type: ApplicationFiled: June 15, 2012Publication date: December 20, 2012Inventors: Daisuke OSHIDA, Masayuki Hirokawa, Akira Yamazaki, Takashi Fujimori, Shigemasa Shiota, Shigeru Furuta
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Publication number: 20120321077Abstract: Provided is a cryptographic communication system including a first semiconductor device and a second semiconductor device. The first semiconductor device includes a common key generation unit that generates a common key CK(a) by using a unique code UC(a) and correction data CD(a), and an encryption unit that encrypts the common key CK(a) generated in the common key generation unit by using a public key PK(b) of the second semiconductor device. The second semiconductor device includes a secret key generation unit that generates a secret key SK(b) by using a unique code UC(b) and correction data CD(b), and a decryption unit that decrypts the common key CK(a) encrypted in the encryption unit by using the secret key SK(b).Type: ApplicationFiled: June 13, 2012Publication date: December 20, 2012Inventors: Shigemasa SHIOTA, Shigeru Furuta, Masayuki Hirokawa, Akira Yamazaki, Daisuke Oshida
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Publication number: 20120213002Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: November 17, 2011Publication date: August 23, 2012Inventors: Kunihiro KATAYAMA, Takayuki TAMURA, Satoshi WATATANI, Kiyoshi INOUE, Shigemasa SHIOTA, Masashi NAITO
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Publication number: 20120176842Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: ApplicationFiled: October 10, 2011Publication date: July 12, 2012Inventors: SHIGEMASA SHIOTA, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
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Patent number: 8219882Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.Type: GrantFiled: May 21, 2008Date of Patent: July 10, 2012Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
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Patent number: 8154939Abstract: In a nonvolatile memory, the threshold is restored to a state before changing, without increasing number of writing undesirably. In a system including a nonvolatile memory, a random number generator, and a controller accessible to the nonvolatile memory, every time access to the nonvolatile memory is performed, the controller determines a refresh-targeted area, based on a random number generated by the random number generator. The controller is made to perform refresh control to re-write to the refresh-targeted area. By such refresh control, the threshold is restored to a state before changing, without increasing the number of writing undesirably.Type: GrantFiled: June 30, 2009Date of Patent: April 10, 2012Assignee: Renesas Electronics CorporationInventors: Yoshinori Mochizuki, Masaharu Ukeda, Shigemasa Shiota
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Patent number: 8103899Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.Type: GrantFiled: October 3, 2008Date of Patent: January 24, 2012Assignee: Renesas Electronics CorporationInventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
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Patent number: 8064257Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: November 10, 2009Date of Patent: November 22, 2011Assignee: Solid State Storage Solutions, Inc.Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 8042021Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.Type: GrantFiled: April 18, 2011Date of Patent: October 18, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota
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Memory system with improved efficiency of data transfer between host, buffer, and nonvolatile memory
Patent number: 8036040Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: GrantFiled: October 14, 2008Date of Patent: October 11, 2011Assignee: Solid State Storage Solutions LLCInventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura -
Patent number: 8015428Abstract: A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.Type: GrantFiled: June 11, 2008Date of Patent: September 6, 2011Assignee: Renesas Electronics CorporationInventors: Yoshinori Mochizuki, Masaharu Ukeda, Shigemasa Shiota