Patents by Inventor Shigemasa Shiota
Shigemasa Shiota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110197108Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.Type: ApplicationFiled: April 18, 2011Publication date: August 11, 2011Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota
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Patent number: 7954039Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.Type: GrantFiled: September 25, 2007Date of Patent: May 31, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota
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Publication number: 20110034124Abstract: A mobile communication terminal device whose authentication and settlement functions by noncontact proximity communication can be continuously used even after operating voltage from battery power drops is provided. Only when the supply of required power from a battery is lost, a security controller is controlled into a mode in which it operates with low power consumption and noncontact authentication and settlement functions are ensured by external electromagnetic field power. Thus the noncontact authentication and settlement functions can be used even after the battery remaining capacity is lost by use of a communication function for the principal purpose.Type: ApplicationFiled: July 18, 2010Publication date: February 10, 2011Inventors: Shigemasa SHIOTA, Kunihiro Katayama, Shinichi Fukasawa, Takeo Kon, Seiji Kobayashi
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Publication number: 20100257313Abstract: A semiconductor device has operation modes selectable through the control by a second microcomputer (113). In a first mode, an operation of a memory controller (105) responding to a memory card command from a memory card interface terminal and an operation of a first microcomputer (106) responding to an IC card command from an IC card interface terminal are separately performed. In a second mode, the first microcomputer operates in response to the IC card command from the IC card interface terminal. In a third mode, the memory controller and the first microcomputer operate in response to an undefined IC card command from the IC card interface terminal. In a fourth mode, the memory controller and the first microcomputer operate in response to the memory card command from the memory card interface terminal. Convenience of the semiconductor device having an IC card function and a memory card function is improved.Type: ApplicationFiled: May 16, 2007Publication date: October 7, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hirotaka Nishizawa, Junichiro Osako, Minoru Shinohara, Tamaki Wada, Kunihirio Katayama, Shigemasa Shiota
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Publication number: 20100177579Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: ApplicationFiled: November 10, 2009Publication date: July 15, 2010Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 7752526Abstract: The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable.Type: GrantFiled: May 14, 2007Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
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Patent number: 7721165Abstract: A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.Type: GrantFiled: November 15, 2006Date of Patent: May 18, 2010Assignee: Solid State Storage Solutions, Inc.Inventors: Takayuki Tamura, Shigemasa Shiota, Kunihiro Katayama, Masashi Naito
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Publication number: 20100054069Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: ApplicationFiled: October 14, 2008Publication date: March 4, 2010Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
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Publication number: 20100034024Abstract: In a nonvolatile memory, the threshold is restored to a state before changing, without increasing number of writing undesirably. In a system including a nonvolatile memory, a random number generator, and a controller accessible to the nonvolatile memory, every time access to the nonvolatile memory is performed, the controller determines a refresh-targeted area, based on a random number generated by the random number generator. The controller is made to perform refresh control to re-write to the refresh-targeted area. By such refresh control, the threshold is restored to a state before changing, without increasing the number of writing undesirably.Type: ApplicationFiled: June 30, 2009Publication date: February 11, 2010Inventors: Yoshinori MOCHIZUKI, Masaharu Ukeda, Shigemasa Shiota
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Patent number: 7616485Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.Type: GrantFiled: October 31, 2007Date of Patent: November 10, 2009Assignee: Solid State Storage Solutions LLCInventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
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Patent number: 7596041Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.Type: GrantFiled: October 3, 2007Date of Patent: September 29, 2009Assignee: Renesas Technology Corp.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
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Patent number: 7552311Abstract: The present invention provides a memory device that can flexibly decide the data to be preread. The memory device according to the present invention includes: a nonvolatile memory; a buffer memory having a higher access speed than the nonvolatile memory; and a control circuit. The control circuit creates a preread data management table that associates a logical address of preread data specified by a preread command inputted from the outside and a buffer memory address for storing the preread data. Moreover, the control circuit reads data specified by the command from the nonvolatile memory and stores it in the buffer memory as preread data. When a logical address specified in a read command inputted from the outside matches a logical address associated by the preread data management table, the control circuit outputs corresponding preread data from the buffer memory.Type: GrantFiled: February 27, 2007Date of Patent: June 23, 2009Assignee: Renesas Technology Corp.Inventors: Fumio Hara, Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya
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Publication number: 20090144834Abstract: A data processing circuit includes a rewritable nonvolatile memory and a controller performing nonvolatile memory control and external interface control. A first detector and a second detector are employed to detect respectively whether the operation of the data processing circuit deviates from a first operating condition and a second operating condition, wherein the second operating condition is severer than the first operating condition. When the first detector detects deviation from the first operating condition, reset is instructed to the controller. When the second detector detects deviation from the second operating condition, the controller backs up an internal state and imposes a restriction on external access to a storage region of the nonvolatile memory.Type: ApplicationFiled: November 14, 2008Publication date: June 4, 2009Inventors: Yoshinori MOCHIZUKI, Masaharu Ukeda, Shigemasa Shiota, Takeo Kon
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Publication number: 20090057417Abstract: The present invention realizes a card on which a secure IC chip (a first semiconductor chip) that operates on both of a high power source voltage and a low power source voltage, and a nonvolatile semiconductor storage chip that operates on the lower power source voltage are mounted. Means for operating the card without exerting an adverse influence of the nonvolatile semiconductor storage chip when the high power source voltage is supplied is realized. A card has a voltage supply interrupting unit which is coupled to a power source terminal to which a first power source voltage and a second power source voltage higher than the first power source voltage are supplied, and a grounding terminal to which a grounding voltage is supplied. The voltage supply interrupting unit, when the first power source voltage is supplied, supplies voltage to a nonvolatile semiconductor storage chip and, when the second power source voltage is supplied, stops supplying the voltage to the nonvolatile semiconductor storage chip.Type: ApplicationFiled: August 26, 2008Publication date: March 5, 2009Inventors: Minoru SHINOHARA, Takeshi Miura, Kanji Mizuno, Shigemasa Shiota, Masayuki Suzuki, Hirotaka Nishizawa
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Publication number: 20090037767Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.Type: ApplicationFiled: October 3, 2008Publication date: February 5, 2009Inventors: SHIGEMASA SHIOTA, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
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Patent number: 7475165Abstract: Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.Type: GrantFiled: February 16, 2005Date of Patent: January 6, 2009Assignee: Renesas Technology Corp.Inventors: Kinji Mitani, Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
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Publication number: 20080313487Abstract: A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control circuit for performing data transfer by using an internal clock generated by the internal oscillator. In the processing device, a clock control circuit that switches a system clock between the internal clock and the external clock in accordance with the interface is provided. When the system clock is switched, the switching is performed after the CPU is set in a sleep state, and after the switching is completed, the sleep state of the CPU is released to restart the operation.Type: ApplicationFiled: June 11, 2008Publication date: December 18, 2008Inventors: Yoshinori MOCHIZUKI, Masaharu Ukeda, Shigemasa Shiota
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Patent number: 7450457Abstract: A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.Type: GrantFiled: April 16, 2007Date of Patent: November 11, 2008Assignee: Solid State Storage Solutions LLCInventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
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Patent number: 7447936Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.Type: GrantFiled: October 19, 2006Date of Patent: November 4, 2008Assignee: Renesas Technology Corp.Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
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Publication number: 20080245878Abstract: Disclosed is a semiconductor device including built-in interface circuits whose operations are selected in response to initialization operation from a host apparatus coupled thereto. In the semiconductor device, a first synchronous interface circuit and a second asynchronous interface circuit using differential signals, share the external terminals of the differential signals (the external differential signal terminals). For example, the semiconductor device adopts an MMC interface circuit as the first interface circuit and a USB interface circuit as the second interface circuit, while keeping the IC card interface function. The semiconductor device selects operations of the adopted interface circuits exclusively. One selection method is to enable an interface operation of the first interface circuit, upon detection of a plurality of edge changes in a clock input from an external clock terminal, which is for initializing the first interface circuit when power supply to the semiconductor device is started.Type: ApplicationFiled: March 18, 2008Publication date: October 9, 2008Inventors: Shigemasa SHIOTA, Shigeo Kurakata, Shinsuke Asari, Tetsuya Iida, Shinichi Fukasawa