Patents by Inventor Shigemasa Shiota

Shigemasa Shiota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7191308
    Abstract: The present invention provides a memory device that can flexibly decide the data to be preread. The memory device according to the present invention includes: a nonvolatile memory; a buffer memory having a higher access speed than the nonvolatile memory; and a control circuit. The control circuit creates a preread data management table that associates a logical address of preread data specified by a preread command inputted from the outside and a buffer memory address for storing the preread data. Moreover, the control circuit reads data specified by the command from the nonvolatile memory and stores it in the buffer memory as preread data. When a logical address specified in a read command inputted from the outside matches a logical address associated by the preread data management table, the control circuit outputs corresponding preread data from the buffer memory.
    Type: Grant
    Filed: March 30, 2004
    Date of Patent: March 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Fumio Hara, Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya
  • Publication number: 20070045426
    Abstract: The present invention is directed to suppress propagation of noise from an interface controller to an IC card microcomputer. A memory card of the invention includes an external terminal, an IC card terminal, an interface controller connected to the external terminal, a memory device connected to the interface controller, and an IC card microcomputer connected to the interface controller. The interface controller controls operation of the memory device and the IC card microcomputer in response to an input from the external terminal. The IC card terminal is directly connected to a connection line between the interface controller and the IC card microcomputer. When operation of the IC card microcomputer responding to an input from the IC card terminal is permitted in parallel with operation responding to an input from the external terminal, the interface controller sets an output buffer in the interface controller connected to the connection line into a high impedance state.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 1, 2007
    Inventors: Shigemasa Shiota, Satoshi Yoshida, Shigeo Kurakata, Shinsuke Asari, Tetsuya Iida
  • Publication number: 20070038901
    Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.
    Type: Application
    Filed: October 19, 2006
    Publication date: February 15, 2007
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
  • Patent number: 7137027
    Abstract: A memory system permitting a number of alternative memory blocks to be made ready in order to extend the rewritable life and thereby contributing to enhanced reliability of information storage is to be provided. The memory system is provided with a nonvolatile memory having a plurality of data blocks in predetermined physical address units and a controller for controlling the nonvolatile memory in response to an access request from outside. Each of the data blocks has areas for holding a rewrite count and error check information regarding each data area. The controller, in a read operation on the nonvolatile memory, checks for any error in the area subject to the read according to error check information and, when there is any error, if the rewrite count is greater than a predetermined value, will replace the pertinent data block with another data block or if it is not greater, correct data in the data block pertaining to the error.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: November 14, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
  • Publication number: 20060239086
    Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.
    Type: Application
    Filed: June 12, 2006
    Publication date: October 26, 2006
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
  • Patent number: 7117328
    Abstract: This invention realizes separate control for each memory area. A memory unit is structured by including a semiconductor memory device capable of memorizing information, the aforementioned memory device is divided into plural memory areas logically and also management table, which is capable of controlling separately each aforementioned memory area for accessing from the outside, is tabled, control information, which prohibits accessing the prescribed memory area of the aforementioned plural memory areas, is provided in the aforementioned management information, and it is prohibited to access the specified memory area from the outside in accordance with control information.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: October 3, 2006
    Assignee: Hitachi ULSI Systems Co., Ltd.
    Inventors: Hirofumi Shibuya, Takayuki Tamura, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
  • Patent number: 7114117
    Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: September 26, 2006
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota
  • Patent number: 7072232
    Abstract: The invention is directed to largely improve reliability by surely protecting data on the basis of an emergency stop request even during a data transfer process. The invention provides a data memory system taking the form of a memory card or the like. When an emergency stop signal requesting an emergency stop is received from an information processor of a host during a read/write data transfer process, a control circuit immediately stops the transfer process and notifies the information processor of end of the read data transfer. At this time, the end of read data transfer is notified irrespective of whether the transfer is finished normally or abnormally. Even when a read data transfer request is received again from the information processor after notifying the information processor of the end of read data transfer, without transferring data, a controller notifies the information processor of an untransferable state of read data.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: July 4, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
  • Publication number: 20060036804
    Abstract: To prevent stored information from being changed even at the occurrence of an abnormal condition in an upstream side of a system due to uncontrollable run of an OS. A nonvolatile storage means having data storage areas and management areas for them in units of predetermined physical addresses has an access protect definition table TLB in a predetermined physical address, and the table has access attribute information defining whether to permit or not access to the data storage areas in association with the physical addresses. The memory system itself possesses access attribute information defining whether to permit or not a write to and a read from the data storage areas in association with addresses to implement an access protect function for write and read. Therefore, the access protect function is maintained even if an abnormal condition occurs in a host device that manages the memory system or controls it as a peripheral circuit.
    Type: Application
    Filed: October 11, 2005
    Publication date: February 16, 2006
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
  • Publication number: 20050248999
    Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.
    Type: Application
    Filed: July 14, 2005
    Publication date: November 10, 2005
    Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
  • Publication number: 20050185449
    Abstract: The present invention is directed to increase noise immunity and largely improve the reliability of a memory device by controlling input/output buffers in accordance with a noise state of input/output signals. When a user data read-transfer request is received from a host, a controller checks the presence or absence of an error in read CRC data. When there is an error in the CRC data due to the influence of noise and the like, a data transfer control unit outputs a control signal to an I/O buffer switching unit to switch I/O buffers to a Schmitt input. If there is no error in the CRC data, the controller transfers user data to the host. When a re-transfer request is sent from the host after the transfer, the controller determines that the data transferred to the host was influenced by noise or the like and the data transfer control unit performs the control of the I/O buffer switching unit to decrease the drivability of the output buffer, thereby reducing noise.
    Type: Application
    Filed: January 14, 2005
    Publication date: August 25, 2005
    Inventors: Shigemasa Shiota, Kinji Mitani, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
  • Publication number: 20050185488
    Abstract: Production cost for a semiconductor data storage apparatus is significantly reduced by using the same controller to support an external analog module and an internal analog module. In a data processing system, a controller is provided with switching elements composed of fuses. Switching between the external analog module composed of an external power supply circuit, an external power supply monitor circuit, and a clock generator element and the internal analog module composed of an internal power supply circuit, an internal power supply monitor circuit, and a self-excited oscillator circuit is performed by arbitrarily disconnecting the fuses. For example, when an internal power supply voltage Vdd1 generated by the external power supply monitor circuit is supplied to the controller or the like, the fuse is disconnected. Thus, measures can be taken in accordance with a purpose by, e.g., selecting the external analog module when an interleave operation is used.
    Type: Application
    Filed: February 16, 2005
    Publication date: August 25, 2005
    Inventors: Kinji Mitani, Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara
  • Patent number: 6931582
    Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: August 16, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
  • Publication number: 20050162929
    Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
    Type: Application
    Filed: March 18, 2005
    Publication date: July 28, 2005
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
  • Patent number: 6882568
    Abstract: The present invention provides a memory system which contributes to improvement in efficiency of a data process accompanying a memory access. A memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an external apparatus, first data transfer between the controller and the external apparatus, second data transfer between the controller and the nonvolatile memory, and third data transfer between the controller and the buffer memory, controls transfer from the controller to the buffer memory in the third data transfer and transfer from the buffer memory to the controller in a time sharing manner, and enables the first data transfer or the second data transfer to be performed in parallel with the transfer carried out in the time sharing manner.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: April 19, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Yasuhiro Nakamura
  • Publication number: 20050033937
    Abstract: This invention realizes separate control for each memory area. A memory unit is structured by including a semiconductor memory device capable of memorizing information, the aforementioned memory device is divided into plural memory areas logically and also management table, which is capable of controlling separately each aforementioned memory area for accessing from the outside, is tabled, control information, which prohibits accessing the prescribed memory area of the aforementioned plural memory areas, is provided in the aforementioned management information, and it is prohibited to access the specified memory area from the outside in accordance with control information.
    Type: Application
    Filed: September 10, 2004
    Publication date: February 10, 2005
    Inventors: Hirofumi Shibuya, Takayuki Tamura, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
  • Publication number: 20040205301
    Abstract: The present invention provides a memory device that can flexibly decide the data to be preread. The memory device according to the present invention includes: a nonvolatile memory; a buffer memory having a higher access speed than the nonvolatile memory; and a control circuit. The control circuit creates a preread data management table that associates a logical address of preread data specified by a preread command inputted from the outside and a buffer memory address for storing the preread data. Moreover, the control circuit reads data specified by the command from the nonvolatile memory and stores it in the buffer memory as preread data. When a logical address specified in a read command inputted from the outside matches a logical address associated by the preread data management table, the control circuit outputs corresponding preread data from the buffer memory.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 14, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Fumio Hara, Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya
  • Publication number: 20040187052
    Abstract: The reliability of data is significantly increased without considerably increasing costs by performing minor data corrections within an information storage device and performing major error corrections in an information processing device. When a request to transfer user data for reading is issued from an information processing device, a control circuit transfers the user data and management data to an error detection circuit, which checks the user data for errors. If the user data contains no error, the control circuit notifies the information processing device that the user data can be transferred, and transfers it to the information processing device. If the user data contains errors, an X count error position and correction data calculation circuit uses the user data and the management data to calculate correction locations and correction data, and judges whether the correction locations are correctable.
    Type: Application
    Filed: November 18, 2003
    Publication date: September 23, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Shigemasa Shiota, Hiroyuki Goto, Hirofumi Shibuya, Fumio Hara, Kinji Mitani
  • Publication number: 20040172581
    Abstract: High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes sector data in one of the first memory and second memory, and next sector data in the other of the first and second memory. Sector data is read out from one of the first memory and second memory to the host computer, and simultaneously, next sector data is read out from the other of the first memory and second memory, and error detection and correction performed in the error correcting means. During a next cycle, the sector data read out from one of the first memory and second memory is outputted to the host computer, and simultaneously, error detection and error correction of the next sector data read out from one of the first computer and second computer is performed in the error correcting means.
    Type: Application
    Filed: December 31, 2003
    Publication date: September 2, 2004
    Inventors: Takayuki Tamura, Shigemasa Shiota, Kunihiro Katayama, Masashi Naito
  • Publication number: 20040158775
    Abstract: It is aimed to detect, notify, and save an abnormal area in semiconductor memory for greatly improving reliability. An inside of semiconductor memories provided for a memory card comprises a user area, a substitution area, an area substitution information storage area, and a management area. An inside of semiconductor memories comprises a user area, a substitution area, and a management area. The user area is a data area a user can use. The substitution area is substituted when an error occurs in the user area. The area substitution information storage area stores area substitution area information. The management area stores substitution information. The information processing section performs substitution on two levels as follows. When detecting an operation indicating a symptom of failure in a semiconductor memory area, the information processing section performs area substitution during an idle state of the memory card.
    Type: Application
    Filed: November 26, 2003
    Publication date: August 12, 2004
    Applicant: Renesas Technology Corp.
    Inventors: Hirofumi Shibuya, Fumio Hara, Hiroyuki Goto, Shigemasa Shiota