Patents by Inventor Shigenobu Maeda

Shigenobu Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190363163
    Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.
    Type: Application
    Filed: August 6, 2019
    Publication date: November 28, 2019
    Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
  • Publication number: 20190355719
    Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.
    Type: Application
    Filed: April 1, 2019
    Publication date: November 21, 2019
    Inventors: Shigenobu MAEDA, Sung Chul PARK, Chul Hong PARK, Yoshinao HARADA, Sung Min KANG, Ji Wook KWON, Ha-Young KIM, Yuichi HIRANO
  • Patent number: 10418448
    Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mirco Cantoro, Zhenhua Wu, Krishna Bhuwalka, Sangsu Kim, Shigenobu Maeda
  • Patent number: 10411129
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park
  • Patent number: 10403717
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions of the substrate that are spaced apart from each other in a direction. The semiconductor device includes an epitaxial layer on the active portions. The semiconductor device includes a metal silicide layer on the epitaxial layer. Moreover, the semiconductor device includes a contact structure that only partially overlaps the metal silicide layer on the epitaxial layer. Related methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Do-Sun Lee, Chang-Woo Sohn, Chul-Sung Kim, Shigenobu Maeda, Young-Moon Choi, Hyo-Seok Choi, Sang-Jin Hyun
  • Publication number: 20190259836
    Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Shigenobu Maeda, Hee-Soo Kang, Sang-Pil Sim, Soo-Hun Hong
  • Patent number: 10319814
    Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Hee-Soo Kang, Sang-Pil Sim, Soo-Hun Hong
  • Patent number: 10304526
    Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
  • Patent number: 10242917
    Abstract: Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: March 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Woo Kim, Shigenobu Maeda, Young-Moon Choi, Yong-Bum Kwon, Chang-Woo Sohn, Do-Sun Lee
  • Publication number: 20190035788
    Abstract: A semiconductor device includes a substrate, a gate structure, a first impurity region, and a second impurity region. The gate structure may cross over a first active region and a second active region of the substrate. The first insulation structure including a first insulation material may be formed on the first active region, and may be spaced apart from opposite sides of the gate structure. The second insulation structure including a second insulation material different from the first insulation material may be formed on the second active region, and may be spaced apart from opposite sides of the gate structure. The first impurity region may be formed at a portion of the first active region between the gate structure and the first insulation structure, and may be doped with p-type impurities. The second impurity region may be formed at a portion of the second active region between the gate structure and the second insulation structure, and may be doped with n-type, impurities.
    Type: Application
    Filed: October 5, 2018
    Publication date: January 31, 2019
    Inventors: MUN-HYEON KIM, SOO-HYEON KIM, BYOUNG-HAK HONG, KEUN-HWI CHO, TOSHINORI FUKAI, SHIGENOBU MAEDA, HIDENOBU FUKUTOME
  • Publication number: 20180308705
    Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: SHIGENOBU MAEDA, Jeong Ju PARK, Eunsung KIM, Hyunwoo KIM, Shiyong YI
  • Patent number: 10032638
    Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Ju Park, Eunsung Kim, Hyunwoo Kim, Shiyong Yi
  • Publication number: 20180197957
    Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu MAEDA, Seunghan SEO, Yeohyun SUNG
  • Publication number: 20180151736
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Inventors: Shigenobu Maeda, Tae-Yong KWON, Sang-Su KIM, Jae-Hoo PARK
  • Patent number: 9966376
    Abstract: Disclosed are CMOS device and CMOS inverter. The CMOS device includes a substrate having active lines extending in a first direction and defined by a device isolation layer, the substrate being divided into an NMOS area, a PMOS area and a boundary area interposed between the NMOS and the PMOS areas and having the device isolation layer without the active line, a gate line extending in a second direction across the active lines and having a first gate structure on the active line in the first area, a second gate structure on the active line in the second and a third gate structure on the device isolation layer in the third area. The electrical resistance and parasitic capacitance of the third gate structure are smaller than those of the NMOS and the PMOS gate structures. Accordingly, better AC and DC performance of the CMOS device can be obtained.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 8, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Mun-Hyeon Kim, Chang-Woo Noh, Keun-Hwi Cho, Myung-Gil Kang, Shigenobu Maeda
  • Patent number: 9941360
    Abstract: A field effect transistor and a semiconductor device including the same are provided. The semiconductor device may include a channel layer, which is provided on a substrate and includes a two-dimensional atomic layer made of a first material, and a source/drain layer, which is provided on the substrate and includes a second material. The first material may be one of phosphorus allotropes, the second material may be one of carbon allotropes, and the channel layer and the source/drain layer may be connected to each other by covalent bonds between the first and second materials.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: April 10, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Seunghan Seo, Yeohyun Sung
  • Patent number: 9899386
    Abstract: In semiconductor devices in which both NMOS devices and PMOS devices are used to perform in different modes such as analog and digital modes, stress engineering is selectively applied to particular devices depending on their required operational modes. That is, the appropriate mechanical stress, i.e., tensile or compressive, can be applied to and/or removed from devices, i.e., NMOS and/or PMOS devices, based not only on their conductivity type, i.e., n-type or p-type, but also on their intended operational application, for example, analog/digital, low-voltage/high-voltage, high-speed/low-speed, noise-sensitive/noise-insensitive, etc. The result is that performance of individual devices is optimized based on the mode in which they operate.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Jeong Hwan Yang
  • Patent number: 9893186
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park
  • Patent number: 9887202
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda, Jihoon Yoon, Sungman Lim
  • Patent number: 9842909
    Abstract: A semiconductor device is provided. The semiconductor device includes a first fin on a substrate, a first gate electrode formed on the substrate to intersect the first fin, a first elevated source/drain on the first fin on both sides of the first gate electrode, and a first metal alloy layer on an upper surface and sidewall of the first elevated source/drain.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: December 12, 2017
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Shigenobu Maeda, Tsukasa Matsuda, Hidenobu Fukutome