Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

Abstract: The program code, when executed by a processor, causes the processor to input fabrication data including a plurality of parameters associated with a semiconductor fabricating process to a framework to generate a first class for analyzing the fabrication data, to extract a first parameter targeted for analysis and a second parameter associated with the first parameter from the plurality of parameters and generate a second class for analyzing the first parameter as a sub class of the first class, to modify the first parameter and the second parameter into a data structure having a format appropriate to store in the second class, so as to be stored in the second class, to perform data analysis on the first parameter and the second parameter, to transform the first parameter and the second parameter into corresponding tensor data, and to input the tensor data to the machine learning model.

Abstract: A semiconductor device is provided and includes a substrate and a stack on the substrate. The stack includes plural active layers that are vertically stacked and spaced apart from each other, and plural gate electrodes that are on the active layers, respectively, and vertically stacked. Each active layer includes a channel layer under a corresponding one of the gate electrodes, and a source/drain layer disposed at a side of the channel layer and electrically connected to the channel layer. The channel layer is made of a two-dimensional atomic layer of a first material.

Abstract: A semiconductor device includes an active fin protruding from a substrate, extending in a first direction, and defined by a device isolation layer. Gate structures intersect the active fin and extend in a second direction. Each of the gate structures includes a gate and gate spacers on side surfaces of the gate. Epitaxial layers are disposed on the active fin, on opposite sides of the gate structure, and include a first epitaxial layer providing a drain region and a second epitaxial layer providing a source region. The gate spacers include a first spacer disposed between the first epitaxial layer and the gate. The first spacer includes a first region extending in a third direction, along a side surface of the gate, and a second region extending from a lower portion of the first region in a direction away from the gate.

Abstract: A display driver integrated circuit (IC) is provided. The display driver IC includes a shift register configured to output a digital signal, and a digital-analog converter configured to receive the digital signal and generate a data voltage corresponding to the digital signal, wherein the digital-analog converter includes a delta-sigma modulator configured to output a modulated signal by receiving the digital signal and a first voltage, and performing delta-sigma modulation on the digital signal using the first voltage, and a level shifter configured to receive the modulated signal and a second voltage higher than the first voltage, and amplify the modulated signal using the second voltage.

Abstract: A method of manufacturing a semiconductor device includes forming an active fin protruding from a substrate and extending in a first direction; forming sacrificial gate patterns intersecting the active fin and extend in a second direction; forming recess regions by etching the active fin on at least one side of each of the sacrificial gate patterns; forming source/drain regions on the recess regions; removing the sacrificial gate patterns to form openings; and forming a gate dielectric layer and a gate electrode such that gate structures are formed to cover the active fin in the openings. The source/drain regions are formed by an epitaxial growth process and an in-situ doping process of doping first conductivity-type impurity elements. In at least one of the source/drain regions, after the in-situ doping process is performed, counter-doping is performed using second conductivity-type impurity elements different from the first conductivity-type impurity elements to decrease carrier concentration.

Abstract: The program code, when executed by a processor, causes the processor to input fabrication data including a plurality of parameters associated with a semiconductor fabricating process to a framework to generate a first class for analyzing the fabrication data, to extract a first parameter targeted for analysis and a second parameter associated with the first parameter from the plurality of parameters and generate a second class for analyzing the first parameter as a sub class of the first class, to modify the first parameter and the second parameter into a data structure having a format appropriate to store in the second class, so as to be stored in the second class, to perform data analysis on the first parameter and the second parameter, to transform the first parameter and the second parameter into corresponding tensor data, and to input the tensor data to the machine learning model.

Abstract: Provided is a semiconductor process modeling system. The semiconductor process modeling system includes a preprocessing component configured to generate tensor data from raw data obtained from semiconductor manufacturing equipment, wherein, when the raw data is expressed as a raw matrix representing values of a plurality of process parameters for each of a plurality of wafers, at least one element of the raw matrix is omitted, when the tensor data is expressed as a tensor matrix representing values of a plurality of preprocessed process parameters for each of the plurality of wafers, the number of omitted elements of the tensor matrix is less than the number of omitted elements of the raw matrix, and the preprocessing component is configured to generate the tensor data by modifying the raw data based on at least one of characteristics of the semiconductor manufacturing equipment and characteristics of the plurality of process parameters.

Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.

Abstract: A display driver integrated circuit (IC) is provided. The display driver IC includes a shift register configured to output a digital signal, and a digital-analog converter configured to receive the digital signal and generate a data voltage corresponding to the digital signal, wherein the digital-analog converter includes a delta-sigma modulator configured to output a modulated signal by receiving the digital signal and a first voltage, and performing delta-sigma modulation on the digital signal using the first voltage, and a level shifter configured to receive the modulated signal and a second voltage higher than the first voltage, and amplify the modulated signal using the second voltage.

Abstract: A semiconductor device is provided and includes a substrate and a stack on the substrate. The stack includes plural active layers that are vertically stacked and spaced apart from each other, and plural gate electrodes that are on the active layers, respectively, and vertically stacked. Each active layer includes a channel layer under a corresponding one of the gate electrodes, and a source/drain layer disposed at a side of the channel layer and electrically connected to the channel layer. The channel layer is made of a two-dimensional atomic layer of a first material.

Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.

Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.

Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.

Abstract: A semiconductor device, a field effect transistor, and a fin field effect transistor are provided. The semiconductor device may include a channel layer, a source/drain layer, and a gate electrode. The channel layer is provided on a substrate and extends in a direction perpendicular to a top surface of the substrate. The source/drain layer is disposed at a side of the channel layer and is electrically connected to the channel layer. The gate electrode is provided adjacent to at least one of surfaces of the channel layer. The channel layer includes a two-dimensional atomic layer made of a first material.

Abstract: A semiconductor device includes an active pattern provided on a substrate and a gate electrode crossing over the active pattern. The active pattern includes a first buffer pattern on the substrate, a channel pattern on the first buffer pattern, a doped pattern between the first buffer pattern and the channel pattern, and a second buffer pattern between the doped pattern and the channel pattern. The doped pattern includes graphene injected with an impurity.

Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.