Patents by Inventor Shigetaka Kasuga

Shigetaka Kasuga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11965987
    Abstract: A driver circuit includes: a first node connected to a first signal line; a first switch transistor provided between a first power supply and a first capacitor; a second switch transistor provided between a second power supply and a second capacitor; a third switch transistor provided between the first capacitor and the first node; and a fourth switch transistor provided between the second capacitor and the first node.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: April 23, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Motonori Ishii, Shigetaka Kasuga
  • Publication number: 20230353906
    Abstract: Effective pixels and a failure detection pixel are connected to a control signal line for controlling an operation of the pixels and to an output signal line for outputting a result of failure detection in the pixels. Among the effective pixels, the effective pixels in a same row are connected in common to a same control signal line, and the effective pixels in a same column are connected in common to a same output signal line. The failure detection pixel is connected in common to at least one of the control signal line or the output signal line and configured to detect a failure in any of the effective pixels connected to the at least one of the control signal line or the output signal line.
    Type: Application
    Filed: June 30, 2023
    Publication date: November 2, 2023
    Inventors: Toru OKINO, Shinzo KOYAMA, Shigeru SAITOU, Masato TAKEMOTO, Masaki TAMARU, Hiroshi KOSHIDA, Shigetaka KASUGA, Yugo NOSE
  • Publication number: 20230156370
    Abstract: A solid-state imaging apparatus includes a plurality of pixel circuits arranged in a matrix. Each pixel circuit includes: a photodiode; a first charge storage that stores a charge; a floating diffusion region that stores a charge; a second charge storage that stores a charge; a first transfer transistor that transfers a charge from the photodiode to the first charge storage; a second transfer transistor that transfers a charge from the first charge storage to the floating diffusion region; a first reset transistor that resets the floating diffusion region; and an accumulating transistor for accumulating a charge of the floating diffusion region in the second charge storage. The capacitance of the first charge storage is greater than the capacitance of the floating diffusion region, and the capacitance of the second charge storage is greater than the capacitance of the floating diffusion region.
    Type: Application
    Filed: January 18, 2023
    Publication date: May 18, 2023
    Inventors: Masaki TAMARU, Shigetaka KASUGA, Shinzo KOYAMA
  • Publication number: 20230131491
    Abstract: A solid-state imaging device includes: pixels; a first sample-and-hold circuit provided per column and generating a first differential voltage that is a difference between a first reset voltage and a first signal voltage output from a first pixel disposed in a corresponding column among the pixels; a second sample-and-hold circuit provided per column and generating a second differential voltage that is a difference between a second reset voltage and a second signal voltage output from a second pixel disposed in the corresponding column among the pixels and different from the first pixel; and an A/D conversion circuit provided per column and converting, into digital signals, a first voltage based on the first differential voltage output from the first sample-and-hold circuit disposed in the corresponding column and a second voltage based on the second differential voltage output from the second sample-and-hold circuit disposed in the corresponding column.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 27, 2023
    Inventors: Shigetaka KASUGA, Masaki TAMARU, Yugo NOSE
  • Publication number: 20220191424
    Abstract: An imaging device includes: a solid-state imaging element having a plurality of pixel cells arranged in a matrix; and a signal processing part configured to process a detection signal outputted from each of the pixel cells. The pixel cells each include an avalanche photodiode and output a voltage corresponding to a count number of photons received by the avalanche photodiode as the detection signal. The signal processing part includes a variation calculation part configured to calculate a variation between the pixel cells in the detection signal outputted from each of the pixel cells, and a correction calculation part configured to correct the detection signal outputted from each of the pixel cells, on the basis of the variation calculated by the variation calculation part.
    Type: Application
    Filed: March 1, 2022
    Publication date: June 16, 2022
    Inventors: Shota YAMADA, Motonori ISHII, Shigetaka KASUGA, Masato TAKEMOTO, Yutaka HIROSE
  • Publication number: 20220182572
    Abstract: An imaging device includes: a solid-state imaging element having a plurality of pixel cells arranged in a matrix; and a control part configured to control the solid-state imaging element. The pixel cells each include an avalanche photodiode, a floating diffusion part configured to accumulate electric charges, a transfer transistor connecting a cathode of the avalanche photodiode and the floating diffusion part, and a reset transistor for resetting electric charges accumulated in the floating diffusion part. The control part controls the reset transistor to discharge electric charges exceeding a predetermined electric charge amount, of electric charges accumulated in the floating diffusion part from the cathode of the avalanche photodiode via the transfer transistor.
    Type: Application
    Filed: February 24, 2022
    Publication date: June 9, 2022
    Inventors: Shota YAMADA, Shigetaka KASUGA, Motonori ISHII, Akito INOUE, Yutaka HIROSE
  • Publication number: 20220057490
    Abstract: A driver circuit includes: a first node connected to a first signal line; a first switch transistor provided between a first power supply and a first capacitor; a second switch transistor provided between a second power supply and a second capacitor; a third switch transistor provided between the first capacitor and the first node; and a fourth switch transistor provided between the second capacitor and the first node.
    Type: Application
    Filed: September 27, 2021
    Publication date: February 24, 2022
    Inventors: Motonori ISHII, Shigetaka KASUGA
  • Publication number: 20220003864
    Abstract: A distance measuring method according to the present disclosure includes: measuring, in an environment where background light is applied to an object, the illuminance of the background light; setting a distance measuring range based on the illuminance of the background light; setting, based on the distance measuring range set, an image capturing condition for an image capturer including a plurality of pixels each including an avalanche photo diode (APD) and an emission condition in which light is emitted from a light source; and measuring a distance to the object by controlling the image capturer and the light source based on the image capturing condition and the emission condition that are set.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 6, 2022
    Inventors: Yugo Nose, Shinzo KOYAMA, Akihiro ODAGAWA, Shigetaka KASUGA, Manabu USUDA
  • Publication number: 20220005855
    Abstract: A plurality of pixel cells are provided on a semiconductor substrate and arranged in a two-dimensional array. At least one of the plurality of pixel cells includes a light receiving part, a pixel circuit, and a second transistor. The light receiving part receives an incident light to generate an electrical charge. The pixel circuit includes first transistors arranged side by side along a first direction and a charge retention part that retains the electrical charge generated by the light receiving part. The pixel circuit outputs a light receiving signal in accordance with the electrical charge generated by the light receiving part. The second transistor connects the charge retention part to a memory part that stores the electrical charge. Seen along a thickness direction of the semiconductor substrate, the second transistor is apart from the first transistors in a second direction orthogonal to the first direction.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Inventors: Masaki TAMARU, Shigetaka KASUGA, Yusuke SAKATA, Mitsuyoshi MORI, Shinzo KOYAMA
  • Publication number: 20220003876
    Abstract: A distance-image obtaining method includes: (A) setting a plurality of distance-divided segments in a depth direction, and (B) obtaining a distance image based on each of the plurality of distance-divided segments set. The obtaining of the distance image includes: obtaining a plurality of distance images by imaging two or more of the plurality of distance-divided segments, to obtain a first distance image group; and obtaining a plurality of distance images by imaging distance-divided segments, among the plurality of distance-divided segments, in a phase different from a phase of the two or more of the plurality of distance-divided segments, to obtain a second distance image group.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 6, 2022
    Inventors: Shigetaka KASUGA, Shinzo KOYAMA, Masaki TAMARU, Hiroshi KOSHIDA, Yugo NOSE, Masato TAKEMOTO
  • Patent number: 11153521
    Abstract: A solid-state image sensor includes a pixel array including pixel cells arranged in a matrix. Each of the pixel cells includes an avalanche photodiode, a floating diffusion which accumulates charges, a transfer transistor which connects a cathode of the avalanche photodiode to the floating diffusion, a first reset transistor for resetting charges collected in the cathode of the avalanche photodiode, a second reset transistor for resetting charges accumulated in the floating diffusion, an amplification transistor for converting a charge amount of charges accumulated in the floating diffusion into a voltage, a memory which accumulates charges, and a count transistor which connects the floating diffusion to the memory.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: October 19, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigetaka Kasuga, Manabu Usuda, Kentaro Nakanishi
  • Publication number: 20210072380
    Abstract: A distance measuring device is to be connected to a wave transmission module to transmit a measuring wave and a wave reception module including a first wave receiver and a second wave receiver, both of which receive the measuring wave reflected from a target. In this distance measuring device, a first wave reception period in which the first wave receiver receives the measuring wave and a second wave reception period in which the second wave receiver receives the measuring wave overlap with each other on a time axis. In addition, in this distance measuring device, a time lag is provided between respective beginning times of the first and second wave reception periods. The time lag is shorter than either the first wave reception period or the second wave reception period.
    Type: Application
    Filed: March 14, 2019
    Publication date: March 11, 2021
    Inventors: Hiroshi KOSHIDA, Shinzo KOYAMA, Motonori ISHII, Shigetaka KASUGA
  • Patent number: 10812729
    Abstract: A solid-state imaging device includes a detector, a count value storage, and a reader. The detector includes an avalanche amplification type light receiving element that detects a photon, and a resetter that resets an output potential of the light receiving element, and outputs a digital signal that indicates the presence or absence of incidence of a photon on the light receiving element. The count value storage performs counting by converting the digital signal output from the detector to an analog voltage, and stores the result of counting as a count value. The reader outputs an analog signal indicating the count value.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: October 20, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigetaka Kasuga, Seiji Yamahira, Yoshihisa Kato
  • Publication number: 20200106982
    Abstract: A solid-state image sensor includes a pixel array including pixel cells arranged in a matrix. Each of the pixel cells includes an avalanche photodiode, a floating diffusion which accumulates charges, a transfer transistor which connects a cathode of the avalanche photodiode to the floating diffusion, a first reset transistor for resetting charges collected in the cathode of the avalanche photodiode, a second reset transistor for resetting charges accumulated in the floating diffusion, an amplification transistor for converting a charge amount of charges accumulated in the floating diffusion into a voltage, a memory which accumulates charges, and a count transistor which connects the floating diffusion to the memory.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 2, 2020
    Inventors: Shigetaka KASUGA, Manabu USUDA, Kentaro NAKANISHI
  • Patent number: 10469774
    Abstract: An imaging apparatus changes a multiplication factor of an avalanche photodiode (APD) at one of (i) a first timing subsequent to an exposure period of a first frame in a first vertical scanning period and a readout period of the first frame in a second vertical scanning period, and previous to an exposure period of a second frame in a third vertical scanning period, and (ii) a second timing subsequent to an exposure period of the first frame in the first vertical scanning period, and previous to a readout period of the first frame and an exposure period of the second frame which are provided in parallel in the second vertical scanning period.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: November 5, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigetaka Kasuga, Tsuyoshi Tanaka
  • Publication number: 20190020836
    Abstract: An imaging apparatus changes a multiplication factor of an avalanche photodiode (APD) at one of (i) a first timing subsequent to an exposure period of a first frame in a first vertical scanning period and a readout period of the first frame in a second vertical scanning period, and previous to an exposure period of a second frame in a third vertical scanning period, and (ii) a second timing subsequent to an exposure period of the first frame in the first vertical scanning period, and previous to a readout period of the first frame and an exposure period of the second frame which are provided in parallel in the second vertical scanning period.
    Type: Application
    Filed: September 5, 2018
    Publication date: January 17, 2019
    Inventors: Shigetaka KASUGA, Tsuyoshi TANAKA
  • Publication number: 20170187939
    Abstract: A solid-state imaging device includes a detector, a count value storage, and a reader. The detector includes an avalanche amplification type light receiving element that detects a photon, and a resetter that resets an output potential of the light receiving element, and outputs a digital signal that indicates the presence or absence of incidence of a photon on the light receiving element. The count value storage performs counting by converting the digital signal output from the detector to an analog voltage, and stores the result of counting as a count value. The reader outputs an analog signal indicating the count value.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Shigetaka KASUGA, Seiji YAMAHIRA, Yoshihisa KATO
  • Patent number: 9570486
    Abstract: A solid-state imaging device includes: a photoelectric conversion unit which converts light into signal charges; an accumulation unit which accumulates the signal charges; a transfer transistor connected between the photoelectric conversion unit and the accumulation unit for transferring to the accumulation unit, the signal charges obtained through the conversion by the photoelectric conversion unit; an amplification transistor for amplifying the signal charges accumulated in the accumulation unit to generate a voltage signal, the amplification transistor having a gate connected to the accumulation unit; a reset transistor for resetting a voltage of the accumulation unit; a first amplification circuit for negatively feeding back the voltage signal generated by the amplification transistor to the reset transistor; and a second amplification circuit for positively feeding back the voltage signal generated by the amplification transistor to the amplification transistor.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: February 14, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Motonori Ishii, Shigetaka Kasuga
  • Patent number: 9554066
    Abstract: A solid-state imaging device includes: pixels arrayed two-dimensionally; pixel common circuits arrayed in a matrix, each shared by adjacent pixels of a certain number among the pixels; column common circuits, each provided for one of columns of the pixel common circuits, and shared by pixel common circuits belonging to a same column; column signal lines each provided for one of the columns of the pixel common circuits; and reset signal lines each provided for one of the columns of the pixel common circuits, in which an electric signal from each of the pixels is detected by a corresponding one of the pixel common circuits and read by a corresponding one of the column common circuits, and the electric signal detected by the corresponding one of the pixel common circuits is reset by a feedback path including one column signal line, one column common circuit, and one reset signal lines.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: January 24, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Motonori Ishii, Shigetaka Kasuga, Mitsuyoshi Mori
  • Patent number: 9319609
    Abstract: A pixel unit included in a sensor chip includes: a first pixel connected to a first feedback amplifier which is connected to a first column signal line as an input line and a first reset drain line as an output line; and a second pixel connected to a second feedback amplifier which is connected to a second column signal line as an input line and a second reset drain line as an output line. A drain of a reset transistor of the first pixel is connected to the first reset drain line, a drain of a reset transistor of the second pixel is connected to the second reset drain line, a source of an amplifying transistor of the first pixel is connected to the first column signal line, and a source of an amplifying transistor of the second pixel is connected to the second column signal line.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: April 19, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shigetaka Kasuga, Motonori Ishii