Patents by Inventor Shigetaka Kasuga
Shigetaka Kasuga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9036064Abstract: A solid-state imaging device in the present disclosure includes a semiconductor substrate, pixels, and column signal lines. Each of the pixels includes an amplifying transistor, a selection transistor, a reset transistor, and a photoelectric converting unit. The photoelectric converting unit includes a photoelectric converting film, a transparent electrode, a pixel electrode, and an accumulation diode. The pixel electrode and the accumulation diode are connected to a gate of the amplifying transistor. The amplifying transistor has a source connected to the column signal line and a drain connected to a power source line. The reset transistor has a source connected to the pixel electrode. The selective transistor is provided between the source of the amplifying transistor and the column signal line. A threshold voltage of the amplifying transistor is lower than a voltage of the accumulation diode.Type: GrantFiled: October 21, 2013Date of Patent: May 19, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Shigetaka Kasuga, Motonori Ishii
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Publication number: 20150103219Abstract: A pixel unit included in a sensor chip includes: a first pixel connected to a first feedback amplifier which is connected to a first column signal line as an input line and a first reset drain line as an output line; and a second pixel connected to a second feedback amplifier which is connected to a second column signal line as an input line and a second reset drain line as an output line. A drain of a reset transistor of the first pixel is connected to the first reset drain line, a drain of a reset transistor of the second pixel is connected to the second reset drain line, a source of an amplifying transistor of the first pixel is connected to the first column signal line, and a source of an amplifying transistor of the second pixel is connected to the second column signal line.Type: ApplicationFiled: December 22, 2014Publication date: April 16, 2015Inventors: Shigetaka KASUGA, Motonori ISHII
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Patent number: 8957983Abstract: A solid-state imaging device includes pixels, vertical signal lines, a high-order AD converter configured to convert M bits, a low-order AD converter, and first and second selection circuits. The first selection circuit is configured to output, in a normal mode, voltage of the selected vertical signal line and to output correction voltage in a correction mode. The high-order AD converter calculates 2M residual voltage values each corresponding to a difference between a signal voltage value and each of 2M threshold voltage values; outputs, in the normal mode, a high-order bit digital value corresponding to the maximum one of the 2M threshold voltage values in a range below the signal voltage value, and outputs voltage having a residual voltage value corresponding to the maximum threshold voltage value; and outputs, in the correction mode, voltage having a residual voltage value corresponding to a selected threshold voltage value.Type: GrantFiled: December 31, 2012Date of Patent: February 17, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Motonori Ishii, Shigetaka Kasuga
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Patent number: 8866059Abstract: A solid-state imaging device that is configurable into a small size appropriate for expanding dynamic range includes: a photodiode which is a photoelectric conversion unit that generates charge by incident light; a MOS transistor which is connected to the photodiode and transfers the charge; a floating diffusion region which is a first accumulation unit which accumulates the charge via the MOS transistor; a MOS transistor which is a second transfer unit connected to the floating diffusion region and connected in series to the MOS transistor; and a MOS transistor which is an output unit which outputs, via the MOS transistor, a signal voltage in accordance with an amount of the charge.Type: GrantFiled: July 23, 2009Date of Patent: October 21, 2014Assignee: Panasonic CorporationInventors: Takahiko Murata, Takayoshi Yamada, Yoshihisa Kato, Shigetaka Kasuga, Mitsuyoshi Mori
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Patent number: 8817143Abstract: A plurality of pixel circuits arranged in rows and columns, and each of which outputs an electric signal according to an amount of received light; a first column signal line provided for each of the columns, and for sequentially transferring the electric signals from said pixel circuits in a corresponding column; and a holding circuit provided for each of the pixel circuits in each column, and which holds the electric signal transferred through the column signal line in the corresponding column are provided. A holding circuit includes a first capacitor which holds a first electric signal of the corresponding pixel circuit in a reset state; and a second capacitor which holds a second electric signal after the corresponding pixel circuit receives light. A difference circuit calculates a difference between two electric signals held by the first capacitor and the second capacitor in a same holding circuit.Type: GrantFiled: October 12, 2011Date of Patent: August 26, 2014Assignee: Panasonic CorporationInventors: Takahiko Murata, Takayoshi Yamada, Yoshihisa Kato, Shigetaka Kasuga
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Publication number: 20140131554Abstract: A solid-state imaging device includes: a photoelectric conversion unit which converts light into signal charges; an accumulation unit which accumulates the signal charges; a transfer transistor connected between the photoelectric conversion unit and the accumulation unit for transferring to the accumulation unit, the signal charges obtained through the conversion by the photoelectric conversion unit; an amplification transistor for amplifying the signal charges accumulated in the accumulation unit to generate a voltage signal, the amplification transistor having a gate connected to the accumulation unit; a reset transistor for resetting a voltage of the accumulation unit; a first amplification circuit for negatively feeding back the voltage signal generated by the amplification transistor to the reset transistor; and a second amplification circuit for positively feeding back the voltage signal generated by the amplification transistor to the amplification transistor.Type: ApplicationFiled: January 22, 2014Publication date: May 15, 2014Applicant: PANASONIC CORPORATIONInventors: Motonori ISHII, Shigetaka KASUGA
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Patent number: 8692177Abstract: A solid-state imaging device includes an imager including pixels arranged in a matrix, and analog to digital (AD) converters, each of which is provided in each pixel column and converts a signal voltage read from one of the pixels located in the column to a digital value. Each of the AD converters includes a comparator and a counter section including a counter circuit, which receives a comparison result of the comparator and includes a first D flip-flop (DFF) for n-bits, and a transfer circuit, which includes a second DFF for n-bits holding and outputting a count value of the counter circuit. The second DFFs provided in the columns are coupled in series to form a transfer section transferring the signal voltage which has been digitally converted.Type: GrantFiled: July 30, 2012Date of Patent: April 8, 2014Assignee: Panasonic CorporationInventors: Shigetaka Kasuga, Motonori Ishii, Sanzo Ugawa, Yusuke Okada
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Publication number: 20140043510Abstract: A solid-state imaging device in the present disclosure includes a semiconductor substrate, pixels, and column signal lines. Each of the pixels includes an amplifying transistor, a selection transistor, a reset transistor, and a photoelectric converting unit. The photoelectric converting unit includes a photoelectric converting film, a transparent electrode, a pixel electrode, and an accumulation diode. The pixel electrode and the accumulation diode are connected to a gate of the amplifying transistor. The amplifying transistor has a source connected to the column signal line and a drain connected to a power source line. The reset transistor has a source connected to the pixel electrode. The selective transistor is provided between the source of the amplifying transistor and the column signal line. A threshold voltage of the amplifying transistor is lower than a voltage of the accumulation diode.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: PANASONIC CORPORATIONInventors: Shigetaka KASUGA, Motonori ISHII
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Publication number: 20130314574Abstract: A solid-state imaging device includes: pixels arrayed two-dimensionally; pixel common circuits arrayed in a matrix, each shared by adjacent pixels of a certain number among the pixels; column common circuits, each provided for one of columns of the pixel common circuits, and shared by pixel common circuits belonging to a same column; column signal lines each provided for one of the columns of the pixel common circuits; and reset signal lines each provided for one of the columns of the pixel common circuits, in which an electric signal from each of the pixels is detected by a corresponding one of the pixel common circuits and read by a corresponding one of the column common circuits, and the electric signal detected by the corresponding one of the pixel common circuits is reset by a feedback path including one column signal line, one column common circuit, and one reset signal lines.Type: ApplicationFiled: August 1, 2013Publication date: November 28, 2013Applicant: Panasonic CorporationInventors: Motonori ISHII, Shigetaka KASUGA, Mitsuyoshi MORI
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Patent number: 8319871Abstract: Provided is a light-receiving chip whose transparent protection plate has an area equal to or smaller than an area of the light-receiving chip, and which does not require a base portion for mounting. Provision of the light-receiving chip contributes to reduction in size and weight of cameras. In addition, provision of a solid-state imaging apparatus having excellent productivity contributes to reduction in price of cameras. A solid-state imaging apparatus (10) having: a solid-state imaging device (11) (a light-receiving chip) provided with a plurality of light-receiving cells arranged either one dimensionally or two dimensionally on one main surface of a base substrate; and a transparent protection plate (12) provided to cover a light-receiving area (18) (the plurality of light-receiving cells), where an area of the transparent protection plate is equal to or smaller than an area of the light-receiving chip, and a space (20) is formed between the light-receiving cells and the transparent protection plate.Type: GrantFiled: November 16, 2010Date of Patent: November 27, 2012Assignee: Panasonic CorporationInventors: Takahiko Murata, Shigetaka Kasuga, Takumi Yamaguti
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Publication number: 20120292485Abstract: A solid-state imaging device includes an imager including pixels arranged in a matrix, and AD converters, each of which is provided in each pixel column and converts a signal voltage read from one of the pixels located in the column to a digital value. Each of the AD converters includes a comparator and a counter section including a counter circuit, which receives a comparison result of the comparator and includes a first DFF for n bits, and a transfer circuit, which includes a second DFF for n bits holding and outputting a count value of the counter circuit. The second DFFs provided in the columns are coupled in series to form a transfer section transferring the signal voltage which has been digitally converted.Type: ApplicationFiled: July 30, 2012Publication date: November 22, 2012Applicant: PANASONIC CORPORATIONInventors: Shigetaka Kasuga, Motonori Ishii, Sanzo Ugawa, Yusuke Okada
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Publication number: 20120033117Abstract: A plurality of pixel circuits arranged in rows and columns, and each of which outputs an electric signal according to an amount of received light; a first column signal line provided for each of the columns, and for sequentially transferring the electric signals from said pixel circuits in a corresponding column; and a holding circuit provided for each of the pixel circuits in each column, and which holds the electric signal transferred through the column signal line in the corresponding column are provided. A holding circuit includes a first capacitor which holds a first electric signal of the corresponding pixel circuit in a reset state; and a second capacitor which holds a second electric signal after the corresponding pixel circuit receives light. A difference circuit calculates a difference between two electric signals held by the first capacitor and the second capacitor in a same holding circuit.Type: ApplicationFiled: October 12, 2011Publication date: February 9, 2012Applicant: PANASONIC CORPORATIONInventors: Takahiko MURATA, Takayoshi YAMADA, Yoshihisa KATO, Shigetaka KASUGA
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Patent number: 8040418Abstract: An object of the present invention is to provide a two-dimensional solid state imaging device which can realize speeding up of signal output. The two-dimensional solid state imaging device includes: a pixel region; a first capacitance element and a second capacitance element each of which is arranged for a different column of pixels and accumulates pixel signals of the corresponding column of pixels; a first horizontal signal line and a second horizontal signal line each of which transmits the pixel signals accumulated in a corresponding capacitance element; a common signal line connected to the horizontal signal lines; a scan timing generation unit and a switch unit which control readout of the pixel signals from the capacitance element to the horizontal signal line; and an external output timing unit and a switch unit which select the horizontal signal line and control output of the pixel signals from the selected horizontal signal line to the common signal line.Type: GrantFiled: July 11, 2006Date of Patent: October 18, 2011Assignee: Panasonic CorporationInventors: Takahiko Murata, Takumi Yamaguchi, Shigetaka Kasuga, Takayoshi Yamada
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Patent number: 8018510Abstract: A solid-state imaging device is provided in which sensitivity is prevented from lowering even when signals of pixels are mixed. The solid-state imaging device includes a plurality of pixel units each of which has a photoelectric conversion element, and is capable of summing signals corresponding to respective outputs of the photoelectric conversion elements of the pixel units. The device includes: a plurality of capacitors, each of which individually accumulates electric charges corresponding to a signal outputted from the associated photoelectric conversion element; and a plurality of MOS transistors which are alternately connected with the associated capacitor. By disconnecting the MOS transistor, the electric charges of the signal outputted from each of the photoelectric conversion elements are accumulated in each associated capacitor, and by conducting the MOS transistors to sum the signals of the pixel units, the capacitors are connected in series.Type: GrantFiled: February 25, 2005Date of Patent: September 13, 2011Assignee: Panasonic CorporationInventors: Takahiko Murata, Takumi Yamaguchi, Shigetaka Kasuga
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Patent number: 7973840Abstract: A solid-state imaging device includes: a plurality of pixels arranged in a matrix, the matrix defining columns of the pixels, and each of the pixels outputting an analog signal by performing photoelectric conversion; an analog-digital converter provided for each of columns which sequentially converts a plurality of analog signals outputted from the pixels in a column into a plurality of digital signals; a memory circuit provided for each column which includes memories and performs, in parallel, a process of storing a one of the digital signals in one of the memories and a process of outputting another of the digital signals previously stored in another of the memories; and data buses connected to the memory in each column.Type: GrantFiled: November 29, 2007Date of Patent: July 5, 2011Assignee: Panasonic CorporationInventors: Shigetaka Kasuga, Takumi Yamaguchi, Takahiko Murata, Takayoshi Yamada
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Patent number: 7968888Abstract: An object of the present invention is to provide a small solid-state image sensor which realizes significant improvement in sensitivity. The solid-state image sensor of the present invention includes a semiconductor substrate in which photoelectric conversion units are formed, a light-blocking film which is formed above the semiconductor substrate and has apertures formed so as to be positioned above respective photoelectric conversion units, and a high refractive index layer formed in the apertures. Here, each aperture has a smaller aperture width than a maximum wavelength in a wavelength of light in a vacuum converted from a wavelength of the light entering the photoelectric conversion unit through the apertures, and the high refractive index is made of a high refractive index material having a refractive index which allows transmission of light having the maximum wavelength through the aperture.Type: GrantFiled: June 7, 2006Date of Patent: June 28, 2011Assignee: Panasonic CorporationInventors: Takumi Yamaguchi, Takahiko Murata, Shigetaka Kasuga
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Patent number: 7956916Abstract: Provided is a solid-state imaging device having pixel units that are two-dimensionally arranged, and including: a photodiode that generates an optical signal charge corresponding to an intensity and an exposure time of light; a MOS transistor that transfers the optical signal charge; an accumulating unit that generates a voltage corresponding to the signal charge through the MOS transistor; a storing unit that stores a voltage corresponding to an optical signal charge in the accumulating unit; and a voltage setting unit that sets a value of a voltage in the accumulating unit to a value corresponding to the voltage in the storing unit.Type: GrantFiled: August 21, 2008Date of Patent: June 7, 2011Assignee: Panasonic CorporationInventors: Takahiko Murata, Yoshihisa Kato, Shigetaka Kasuga, Takayoshi Yamada
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Publication number: 20110121162Abstract: A solid-state imaging device that is configurable into a small size appropriate for expanding dynamic range includes: a photodiode which is a photoelectric conversion unit that generates charge by incident light; a MOS transistor which is connected to the photodiode and transfers the charge; a floating diffusion region which is a first accumulation unit which accumulates the charge via the MOS transistor; a MOS transistor which is a second transfer unit connected to the floating diffusion region and connected in series to the MOS transistor; and a MOS transistor which is an output unit which outputs, via the MOS transistor, a signal voltage in accordance with an amount of the charge.Type: ApplicationFiled: July 23, 2009Publication date: May 26, 2011Applicant: PANASONIC CORPORATIONInventors: Takahiko Murata, Takayoshi Yamada, Yoshihisa Kato, Shigetaka Kasuga, Mitsuyoshi Mori
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Publication number: 20110109779Abstract: Provided is a light-receiving chip whose transparent protection plate has an area equal to or smaller than an area of the light-receiving chip, and which does not require a base portion for mounting. Provision of the light-receiving chip contributes to reduction in size and weight of cameras. In addition, provision of a solid-state imaging apparatus having excellent productivity contributes to reduction in price of cameras. A solid-state imaging apparatus (10) having: a solid-state imaging device (11) (a light-receiving chip) provided with a plurality of light-receiving cells arranged either one dimensionally or two dimensionally on one main surface of a base substrate; and a transparent protection plate (12) provided to cover a light-receiving area (18) (the plurality of light-receiving cells), where an area of the transparent protection plate is equal to or smaller than an area of the light-receiving chip, and a space (20) is formed between the light-receiving cells and the transparent protection plate.Type: ApplicationFiled: November 16, 2010Publication date: May 12, 2011Applicant: PANASONIC CORPORATIONInventors: Takahiko MURATA, Shigetaka KASUGA, Takumi YAMAGUTI
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Patent number: 7940318Abstract: A solid-state imaging device that enables more images to be photographed and a reading time to be shortened by effectively using storage cells is provided. By combining pieces of information which correspond to signal charges output from a photoelectric converter and are sequentially stored in storage cells, it is possible to store more pieces of information than the number of storage cells. Also, by reading the combined information stored in one storage cell, it is possible to read more pieces of information by a single reading operation.Type: GrantFiled: August 9, 2007Date of Patent: May 10, 2011Assignee: Panasonic CorporationInventors: Takayoshi Yamada, Takumi Yamaguchi, Takahiko Murata, Shigetaka Kasuga