Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.

Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer, a bottom electrode over the Nth metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M)th metal layer over the Nth metal layer. N and M are positive integers. The (N+M)th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

Abstract: An integrated circuits device includes a semiconductor substrate having a logic region and a memory region separated by an isolation region having an isolation structure of dielectric material. A memory device is formed on the memory region and includes a gate electrode over a gate dielectric. A dummy gate structure is formed on the isolation structure. The dummy gate structure has a dummy gate electrode layer corresponding to the gate electrode and a dummy gate dielectric layer corresponding to the gate dielectric. A tapered sidewall structure is formed on a logic region-facing side of the dummy gate structure. The tapered sidewall structure is spaced above the isolation structure and either adjacent to or contiguous with the dummy gate electrode layer.

Abstract: The present disclosure provides a semiconductor structure including a first electrode via, a first electrode on the first electrode via, a magnetic tunneling junction (MTJ) over the first electrode, a second electrode over the MTJ, a first dielectric layer on a top surface of the first electrode via, a second dielectric layer over the first electrode, the MTJ, the second electrode, and the first dielectric layer. A sidewall of the MTJ is in contact with the second dielectric layer.

Abstract: A method of making a magnetoresistive random access memory (MRAM) device includes forming a bottom conductive layer. The method includes forming an anti-ferromagnetic layer over the bottom conductive layer and forming a tunnel layer over the anti-ferromagnetic layer. The method includes forming a free magnetic layer, having a magnetic moment aligned in a direction that is adjustable by applying an electromagnetic field, over the tunnel layer, wherein the anti-ferromagnetic layer, the tunnel layer and the free magnetic layer are part of a magnetic tunnel junction (MTJ) unit. The method includes forming a top conductive layer over the free magnetic layer. The method includes performing at least one lithographic process to remove portions of the bottom conductive layer, the MTJ unit and the top conductive layer that is uncovered by a photoresist layer. The method includes removing a portion of a sidewall of the MTJ unit.

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes (1) providing a substrate, (2) depositing a first electrode layer over the substrate, (3) depositing a magnetic tunneling junction (MTJ) layer on the first electrode layer, (4) depositing a second electrode layer on the MTJ layer, (5) patterning the first electrode layer, the MTJ layer and the second electrode layer to form a first electrode, an MTJ and a second electrode, (6) forming a first dielectric layer over the first electrode, the MTJ, and the second electrode, (7) removing a portion of the first dielectric layer, (8) forming a second dielectric layer over the first electrode, the MTJ, the second electrode, and an unremoved portion of the first dielectric layer. A semiconductor structure is also disclosed.

Abstract: Various embodiments of the present application are directed to a method for forming an embedded memory boundary structure with a boundary sidewall spacer. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A multilayer film is formed covering the semiconductor substrate. A memory structure is formed on the memory region from the multilayer film. An etch is performed into the multilayer film to remove the multilayer film from the logic region, such that the multilayer film at least partially defines a dummy sidewall on the isolation structure. A spacer layer is formed covering the memory structure, the isolation structure, and the logic region, and further lining the dummy sidewall. An etch is performed into the spacer layer to form a spacer on dummy sidewall from the spacer layer. A logic device structure is formed on the logic region.

Abstract: A method of planarizing a semiconductor device includes forming a first region and a second region on a semiconductor substrate. The first region has a larger thickness than a thickness of the second region. An interlayer dielectric layer is conformally deposited on the first region and the second region. A photoresist is formed on the second region. A bottom anti-reflective coating layer is formed on the photoresist, first region and second region. A planarization process is performed to the semiconductor substrate. The planarization process to the first region and the second region includes removing portions of the interlayer dielectric layer, the photoresist and the BARC layer.

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a plurality of dielectric layers and a plurality of metal layers that are stacked over one another in alternating fashion. The plurality of metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A dielectric layer is disposed over an upper surface of the bottom electrode. A top electrode is disposed over an upper surface of the dielectric layer and is in direct electrical contact with a lower surface of the upper metal layer.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices include a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Abstract: A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.

Abstract: A method includes forming first and second gate stacks over a substrate. Each of the first and second gate stacks includes a tunneling dielectric layer, a floating gate over the tunneling dielectric layer, a middle dielectric layer over the floating gate, and a control gate over the middle dielectric layer. A conductive layer is formed over the first and second gate stacks. The conductive layer is etched to form a erase gate between the first and second gate stacks. Etching the conductive layer is performed such that a top surface of the erase gate is not higher than a top surface of the control gate and such that the top surface of the erase gate is at least partially curved inwards.

Abstract: A device includes a first conductive via plug, a first electrode, a storage element, a second electrode, a spacer, a barrier structure, a first dielectric layer. The first electrode is over the first conductive via plug. The storage element is over the first electrode. The second electrode is over the storage element. The spacer has a bottom portion extending along a top surface of the first electrode and a standing portion extending from the bottom portion and along a sidewall of the second electrode. The barrier structure extends from the bottom portion of the spacer and along a sidewall of the standing portion of the spacer. The first dielectric layer is substantially conformally over the spacer and the barrier structure.

Abstract: A method for fabricating a semiconductor memory device is provided. The method includes: etching a first region of the semiconductor memory device to expose a first capping layer; forming a second capping layer on the first capping layer; etching a portion of the first capping layer and a portion of the second capping layer to form a first trench reaching a first metal line; and forming a second metal line in the first trench to contact the first metal line.

Abstract: Present disclosure provides a method for manufacturing a semiconductor device, including providing a substrate, forming a first III-V compound layer over the substrate, forming a first passivation layer over the first III-V compound layer, forming a first opening from a top surface of the first passivation layer to the first III-V compound layer, each opening having a stair-shaped sidewall at the first passivation layer, depositing a metal layer over the first passivation layer and in the first opening, the metal layer having a second opening above the corresponding first opening, and removing a portion of the metal layer to form a source electrode and a drain electrode.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a sacrificial spacer over a substrate and forming a select gate along a side of the sacrificial spacer. An inter-gate dielectric is formed over the select gate and the sacrificial spacer. A memory gate layer is formed over the inter-gate dielectric and the sacrificial spacer. The memory gate layer is laterally separated from the sacrificial spacer by the select gate. The memory gate layer is etched to define a memory gate having a topmost point below a top of the sacrificial spacer.

Abstract: A semiconductor arrangement is provided comprising a guard region. The semiconductor arrangement comprises an active region disposed on a first side of the guard region. The active region comprises an active device. The guard region of the semiconductor arrangement comprises residue from the active region. A method of forming a semiconductor arrangement is also provided.

Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.