Patents by Inventor Shih-Chieh Lin
Shih-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145020Abstract: A circuit for testing a memory is provided. An input end of the memory is coupled to a register, and the circuit for testing the memory transmits data to the memory through the register. The circuit for testing the memory performs the following operations sequentially: writing a first data into a target address of the memory, all bits of the target address being at the same level, and all bits of the first data being at the same level; writing a second data to the target address of the memory, all bits of the second data being at the same level, and the second data being different from the first data; reading from the target address an output data; and determining whether the output data is correct.Type: ApplicationFiled: August 22, 2023Publication date: May 2, 2024Inventors: SHENG-LIN LIN, SHIH-CHIEH LIN
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Publication number: 20240146205Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.Type: ApplicationFiled: September 23, 2023Publication date: May 2, 2024Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
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Publication number: 20240145298Abstract: Structures with doping free connections and methods of fabrication are provided. An exemplary structure includes a substrate; a first region of a first conductivity type formed in the substrate; an overlying layer located over the substrate; a well region of a second conductivity type formed in the overlying layer; a conductive plug laterally adjacent to the well region and extending through the overlying layer to electrically contact with the first region; and a passivation layer located between the conductive plug and the well region.Type: ApplicationFiled: February 17, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Min Huang, Tzu-Jui Wang, Jung-I Lin, Hung-Chang Chien, Kuan-Chieh Huang, Tzu-Hsuan Hsu, Chen-Jong Wang
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Patent number: 11974367Abstract: A lighting device includes a light board and a light dimmer circuit. The light board includes multiple first light emitting elements and second light emitting elements. The first light emitting elements are disposed in a first area of the light board. The second light emitting elements are disposed in a second area of the light board. The light dimmer circuit is configured to drive the second light emitting elements to generate flickering lights from the second area of the light board, and is configured to drive the first light emitting elements to generate non-flickering lights from the first area of the light board.Type: GrantFiled: October 4, 2022Date of Patent: April 30, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chih-Hsien Wang, Ming-Chieh Cheng, Po-Yen Chen, Shih-Chieh Chang, Kuan-Hsien Tu, Xiu-Yi Lin, Ling-Chun Wang
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Publication number: 20240136463Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Applicant: EPISTAR CORPORATIONInventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
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Publication number: 20240125982Abstract: A metalens including a transparent substrate and lenses is provided. The lenses are located on the transparent substrate. Each of the lenses includes first columnar microstructures continuously arranged along a first direction and second columnar microstructures continuously arranged along a second direction. A pitch of the first columnar microstructure is different from a pitch of the second columnar microstructure.Type: ApplicationFiled: November 18, 2022Publication date: April 18, 2024Applicant: GUANGZHOU LUXVISIONS INNOVATION TECHNOLOGY LIMITEDInventors: Tzu-Yao Lin, Shih-Chieh Yen
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Patent number: 11961745Abstract: The present disclosure describes an apparatus for processing one or more objects. The apparatus includes a carrier configured to hold the one or more objects, a tank filled with a processing agent and configured to receive the carrier, and a spinning portion configured to contact the one or more objects and to spin the one or more objects to disturb a flow field of the processing agent.Type: GrantFiled: July 18, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Yu Lin, Shih-Chi Kuo, Chun-Chieh Mo
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Publication number: 20240120388Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
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Patent number: 11955515Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.Type: GrantFiled: July 28, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11935611Abstract: The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.Type: GrantFiled: April 12, 2022Date of Patent: March 19, 2024Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Sheng-Lin Lin, Shih-Chieh Lin
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Patent number: 11926266Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.Type: GrantFiled: August 26, 2022Date of Patent: March 12, 2024Assignee: PEGATRON CORPORATIONInventors: Shih-Wei Yeh, Chien-Chih Lin, Yi-Ming Chou, Chun-Chieh Chang
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Publication number: 20240079524Abstract: A semiconductor device comprises a first semiconductor structure, a second semiconductor structure located on the first semiconductor structure, and an active layer located between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure has a first conductivity type, and includes a plurality of first layers and a plurality of second layers alternately stacked. The second semiconductor structure has a second conductivity type opposite to the first conductivity type. The plurality of first layers and the plurality of second layers include indium and phosphorus, and the plurality of first layers and the plurality of second layers respectively have a first indium atomic percentage and a second indium atomic percentage. The second indium atomic percentage is different from the first indium atomic percentage.Type: ApplicationFiled: September 6, 2023Publication date: March 7, 2024Inventors: Wei-Jen HSUEH, Shih-Chang LEE, Kuo-Feng HUANG, Wen-Luh LIAO, Jiong-Chaso SU, Yi-Chieh LIN, Hsuan-Le LIN
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Publication number: 20240077409Abstract: A chiral molecule detector includes a light source, a photodetector, and a carrier. The carrier is configured to reflect at least part of light emitted by the light source to the photodetector. The carrier includes a substrate and a metal reflective layer. An upper surface of the substrate has a periodic hole array containing multiple holes. The metal reflective layer is located on the upper surface of the substrate, and covers a sidewall of the hole and a bottom surface of the hole.Type: ApplicationFiled: November 28, 2022Publication date: March 7, 2024Applicant: GUANGZHOU LUXVISIONS INNOVATION TECHNOLOGY LIMITEDInventors: Tzu-Yao Lin, Shih-Chieh Yen
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Patent number: 11921530Abstract: A power supply system includes an output terminal, a power supply control chip, a power supply switch and a detection device. The power supply control chip is configured to adjust the amount of an input power providing to an electronic device by the power supply device. The power supply switch is configured to control the connection between the power supply device and the power supply control chip. The detection device is configured to detect whether the power supply control chip operates normally. When the power supply control chip operates abnormally, the detection device controls the connection between the power supply device and the power supply control chip through the power supply switch for restarting the power supply control chip. The power supply control chip, the power supply switch and the detection device are disposed in an enclosed space.Type: GrantFiled: July 22, 2021Date of Patent: March 5, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Shih-Chung Wang, Cheng-Yu Shu, Wei-Chieh Lin
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Patent number: 11915977Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.Type: GrantFiled: April 12, 2021Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Ting Tsai, Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Chih-Hui Huang, Sheng-Chau Chen, Shih Pei Chou, Chia-Chieh Lin
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Patent number: 11832029Abstract: A projection system and a projection image adjustment method thereof are provided. The projection image adjustment method is applicable to a processing device connected to multiple projectors, a display, and an input device, and includes the following steps. Arrangement information between the multiple projectors is obtained. Multiple adjustable areas corresponding to a projection image of each projector are simultaneously displayed on the display and the multiple adjustable areas are simultaneously displayed on projection images of the multiple projectors according to the arrangement information. A parameter setting interface corresponding to a first adjustable area among the multiple adjustable areas is displayed on the display. The first adjustable area corresponds to a first projector among the multiple projectors.Type: GrantFiled: October 23, 2020Date of Patent: November 28, 2023Assignee: Coretronic CorporationInventors: Shih-Chieh Lin, Chen-Ming Li, Kang-Shun Hsu, Chia-Yen Ou
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Patent number: 11776648Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.Type: GrantFiled: December 1, 2021Date of Patent: October 3, 2023Assignee: REALTEK SEMICONDUCTOR CORPORATIONInventors: Sheng-Lin Lin, Chun-Yi Kuo, Shih-Chieh Lin
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Publication number: 20230230652Abstract: A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.Type: ApplicationFiled: July 22, 2022Publication date: July 20, 2023Inventors: Shih-Chieh LIN, Sheng-Lin LIN, Li-Wei DENG
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Patent number: D1018891Type: GrantFiled: December 13, 2021Date of Patent: March 19, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Chih-Hsien Wang, Shih-Chieh Chang, Peng-Hui Wang, Ming-Chieh Cheng, Xiu-Yi Lin