Abstract: An etching method of etching apparatus is disclosed. The etching apparatus performs an etching process on a material to be processed which includes a material layer and a mask layer formed on the material layer. The etching method includes the following steps. The mask layer is etched. A light intensity at a specific wavelength for light generated is detected when the etching process is performed on the mask layer to be processed and an end point detection signal is generated. An etching completion time of the mask layer to be etched is determined according to the end point detection signal. A thickness of the mask layer to be etched is calculated according to the etching completion time. An etching time of the material layer is adjusted according to the thickness of the mask layer to be etched. The material layer is etched after adjusting the etching time.

Abstract: A memory structure includes: a substrate including a memory array region and a peripheral circuit region; a plurality of bit line structures disposed in the memory array region of the substrate; a dummy bit line structure disposed on the substrate, wherein the dummy bit line structure is disposed in the memory array region and immediately adjacent to the peripheral circuit region; a plurality of contacts disposed between the bit line structures and in the memory array region; a dielectric layer disposed on the substrate and in the peripheral circuit region; and a protective structure disposed in the memory array region and immediately adjacent to the peripheral circuit region, wherein the protective structure includes the dummy bit line structure and a top surface of the protective structure is higher than top surfaces of the bit line structures.

Abstract: A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.

Abstract: Disclosed are a gait analysis method, a gait analysis device, and a computer-readable storage medium. The method includes: obtaining consecutive N motion data; determining a plurality of probability distributions based on the N motion data, wherein the probability distributions respectively corresponds to a plurality of gait events; and determining an event time point of each gait event belonging to a specific step according to the plurality of probability distributions.

Abstract: A method (100) for transferring a patient from a first healthcare environment to a second healthcare environment, comprising: (i) providing (110) a composite network configured to obtain and communicate first information about one or more healthcare assets associated with the patient, and monitoring information about the patient: (ii) receiving (120) a request for the first information and the monitoring information: (iii) communicating (130) the first information and the monitoring information: (iv) configuring (140) one or more healthcare assets in the second healthcare-environment in preparation for a transfer: (v) determining (150) whether the second healthcare environment is ready for the transfer of the patient from the first healthcare environment: (vi) communicating (160) a signal indicating a result of the determining step: and (vii) receiving (180) the patient at the second healthcare environment, or delaying the patient from being transferred to the second healthcare environment.

Abstract: A lead frame includes: a die pad having a die disposing area; a plurality of lead pads located around the die pad; an outer frame, located at a periphery of the die pad and the lead pads; and at least two tie bars, respectively connected between the outer frame and two opposite sides of the die pad. At least one of the die pad and the tie bars includes a thermal deformation mitigation structure.

Abstract: A package structure, includes: a lead frame, having a die pad and lead pads around the die pad; a chip die on the die pad, wherein the lead pads are electrically connected with the chip die via lead wires; a thermal conductive adhesive layer on the chip die; a thermal conductive plate on the thermal conductive adhesive layer; and a packaging material, encapsulating the lead frame, the chip die, the thermal conductive plate, and the thermal conductive adhesive layer. The thermal conductive plate is exposed on a top of the package material, and the lead frame is exposed on a bottom surface of the package material. The package structure has an upper thermal conduction path passing through the chip die, the thermal conductive adhesive layer, and the thermal conductive plate; and a lower thermal conduction path passing through the chip die and the lead frame.

Abstract: A circuit for testing a memory is provided. An input end of the memory is coupled to a register, and the circuit for testing the memory transmits data to the memory through the register. The circuit for testing the memory performs the following operations sequentially: writing a first data into a target address of the memory, all bits of the target address being at the same level, and all bits of the first data being at the same level; writing a second data to the target address of the memory, all bits of the second data being at the same level, and the second data being different from the first data; reading from the target address an output data; and determining whether the output data is correct.

Abstract: The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

Abstract: A projection system and a projection image adjustment method thereof are provided. The projection image adjustment method is applicable to a processing device connected to multiple projectors, a display, and an input device, and includes the following steps. Arrangement information between the multiple projectors is obtained. Multiple adjustable areas corresponding to a projection image of each projector are simultaneously displayed on the display and the multiple adjustable areas are simultaneously displayed on projection images of the multiple projectors according to the arrangement information. A parameter setting interface corresponding to a first adjustable area among the multiple adjustable areas is displayed on the display. The first adjustable area corresponds to a first projector among the multiple projectors.

Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Abstract: A testing system includes a plurality of memory circuits and a testing circuit. The testing circuit is coupled to the memory circuits. The testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation. The testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other.

Abstract: A contact resistance test method and related devices are provided. When a MOS transistor working in a linear region is tested, a functional relationship between the channel width of the MOS transistor and total resistances of the MOS transistor at sampling temperatures is determined, to determine the contact resistance of the MOS transistor at the sampling temperatures. A calibration coefficient of the contact resistance at a current ambient temperature is determined based on the contact resistance of the MOS transistor at the sampling temperatures. A measurement result of the contact resistance is further adjusted based on the calibration coefficient of the contact resistance at the current ambient temperature, to obtain an accurate contact resistance at the current ambient temperature.

Abstract: A method and apparatus for device simulation are provided. The method includes: establishing a simulation model of a to-be-detected device, where the to-be-detected device includes a first resistor and a parasitic resistor, the parasitic resistor includes a second resistor and a contact resistor, the first resistor is a bulk resistor of the to-be-detected device, the second resistor is a terminal resistor of the to-be-detected device, and the contact resistor is an equivalent resistor of a contact plug on the to-be-detected device; determining temperature coefficients of resistance corresponding to the first resistor, the second resistor, and the contact resistor, and adding the temperature coefficients of resistance to the simulation model; and performing device simulation of Simulation Program with Integrated Circuit Emphasis (SPICE) according to the simulation model.

Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

Abstract: The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

Abstract: A contact resistance test method and related devices are provided. When a MOS transistor working in a linear region is tested, a functional relationship between the channel width of the MOS transistor and total resistances of the MOS transistor at sampling temperatures is determined, to determine the contact resistance of the MOS transistor at the sampling temperatures. A calibration coefficient of the contact resistance at a current ambient temperature is determined based on the contact resistance of the MOS transistor at the sampling temperatures. A measurement result of the contact resistance is further adjusted based on the calibration coefficient of the contact resistance at the current ambient temperature, to obtain an accurate contact resistance at the current ambient temperature.

Abstract: The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.

Abstract: An etching method of etching apparatus is disclosed. The etching apparatus performs an etching process on a material to be processed which includes a material layer and a mask layer formed on the material layer. The etching method includes the following steps. The mask layer is etched. A light intensity at a specific wavelength for light generated is detected when the etching process is performed on the mask layer to be processed and an end point detection signal is generated. An etching completion time of the mask layer to be etched is determined according to the end point detection signal. A thickness of the mask layer to be etched is calculated according to the etching completion time. An etching time of the material layer is adjusted according to the thickness of the mask layer to be etched. The material layer is etched after adjusting the etching time.

Abstract: A medical device (10) for use in a Magnetic Resonance environment includes a keypad (22) having keys (24). Light sources (26) are disposed with respective keys of the keypad to illuminate the respective keys. At least one electronic processor (18) is programmed to: perform user interfacing operations in which user inputs are received via the keypad; during the user interfacing operations, control the light sources to selectively illuminate keys usable in the user interfacing operations; and controlling or configuring the medical device in accord with the user inputs received during the user interfacing operations.