Abstract: A method for forming a memory structure includes: providing a substrate including a memory array region and a peripheral circuit region; forming a plurality of bit line structures in the memory array region; forming a dielectric layer in the peripheral circuit region; forming a plurality of contacts between the bit line structures; depositing a protective layer on the substrate; depositing a hard mask layer on the protective layer; etching back the hard mask layer to form a hard mask spacer on the first top surface of the protective layer and immediately adjacent to the peripheral circuit region; and etching the protective layer with the hard mask spacer as an etching mask to leave a protective feature at the boundary between the memory array region and the peripheral circuit region.

Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

Abstract: A method for forming a memory structure includes: providing a substrate including a memory array region and a peripheral circuit region; forming a plurality of bit line structures in the memory array region; forming a dielectric layer in the peripheral circuit region; forming a plurality of contacts between the bit line structures; depositing a protective layer on the substrate; depositing a hard mask layer on the protective layer; etching back the hard mask layer to form a hard mask spacer on the first top surface of the protective layer and immediately adjacent to the peripheral circuit region; and etching the protective layer with the hard mask spacer as an etching mask to leave a protective feature at the boundary between the memory array region and the peripheral circuit region.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A dual membrane restrictor adapted to be connected to an oil supplying device, a loading device, and a recycling device is provided. The dual membrane restrictor includes a casing and first and second membranes. The casing has a first channel connected to the oil supplying device, first and second chambers, a second channel connected to the loading device, and a third channel connected to the recycling device. The first membrane is disposed in the first chamber divided into first upper and lower chambers by the first membrane. The first channel is connected to the first upper chamber. The second membrane is disposed in the second chamber divided into second upper and lower chambers by the second membrane. The second upper chamber is connected to the first lower chamber and the second channel. The second lower chamber is connected to the second channel and the third channel.

Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

Abstract: A projection system and a projection image adjustment method thereof are provided. The projection image adjustment method is applicable to a processing device connected to multiple projectors, a display, and an input device, and includes the following steps. Arrangement information between the multiple projectors is obtained. Multiple adjustable areas corresponding to a projection image of each projector are simultaneously displayed on the display and the multiple adjustable areas are simultaneously displayed on projection images of the multiple projectors according to the arrangement information. A parameter setting interface corresponding to a first adjustable area among the multiple adjustable areas is displayed on the display. The first adjustable area corresponds to a first projector among the multiple projectors.

Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A hydrostatic bearing assembly including a bearing and two membrane throttles is provided. The bearing is adapted to be movably disposed on a slide rail and includes two sub-bearing portions that are disposed opposite to each other on two opposite sides of the slide rail. The two membrane throttles are adapted to be connected to a pump. The pump is adapted to supply a fluid through the two membrane throttles to flow between the two sub-bearing portions and the slide rail, and each of the membrane throttles includes a casing and a throttling membrane piece. At least one of the casing and the corresponding sub-bearing portion includes a chamber, an inlet and an outlet communicating with the chamber, and an outlet surface, wherein the pump is adapted to be connected to the inlet, and the slide rail is adapted to be disposed adjacent to the outlet. The throttling membrane piece is being positioned in the chamber covers on the outlet surface.

Abstract: A method for power management by a rack management controller (RMC) of a server rack includes collecting power consumption data from a first baseboard management controller (BMC) of a first server in the server rack and sending the power consumption data to a management server. The RMC receives power requirements from the management server and determines a power setting based on the power consumption data and the power requirements. The RMC requests the first BMC to limit power consumption of the first server according to the power setting.

Abstract: A medical device (10) for use in a Magnetic Resonance environment includes a keypad (22) having keys (24). Light sources (26) are disposed with respective keys of the keypad to illuminate the respective keys. At least one electronic processor (18) is programmed to: perform user interfacing operations in which user inputs are received via the keypad; during the user interfacing operations, control the light sources to selectively illuminate keys usable in the user interfacing operations; and controlling or configuring the medical device in accord with the user inputs received during the user interfacing operations.

Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

Abstract: A membrane restrictor adapted to be connected to a pump and a bearing is provided. The pump is adapted to supply fluid to a location between the bearing and the rail through the membrane. The bearing is adapted to be disposed on a rail. The membrane restrictor includes a casing and a membrane. The casing has a chamber, an inlet and an outlet communicating with each other through the chamber, and a restricting plane. The pump is adapted to be connected to the inlet; the bearing is adapted to be connected to the outlet. The membrane is disposed in the chamber. The restricting plane is an inner surface of the casing adjacent to the outlet and towards the membrane. Dimensionless stiffness of the membrane is Kr*, and 1.33?Kr*?2. Kr*=KrL0/(psAr). Here, Kr is stiffness of the membrane, L0 is a distance from the membrane to the restricting plane when no fluid is supplied by the pump (i.e., assembling clearance of the membrane), ps is pressure supplied by the pump, and Ar is an effective area of the restricting plane.

Abstract: A MEMS device includes: a substrate; a proof mass suspended over the substrate, the proof mass including at least one proof mass body and a proof mass frame connected to and accommodating the proof mass body, the proof mass frame including at least one self-test frame; and at least one self-test electrode inside the self-test frame, and connected to the substrate; wherein when a voltage difference is applied between the self-test electrode and the self-test frame, the proof mass is driven to have an in-plane movement, and wherein the self-test electrode and the self-test frame do not form a sensing capacitor in between.

Abstract: A driving circuit in this disclosure includes plural stages of shift register circuits. Every stage in the shift register circuits includes an enabling control circuit, a first output circuit, a second output circuit and a disabling control circuit. The enabling circuit is configured to control the voltage of the first operation node according to enabling signal. The first output unit is configured to generate the first driving signal according to the voltage of the first operation node and the first clock signal. The second output unit is configured to generate the second driving signal according to the voltage of the first operation node and the second clock signal. The disabling control unit is used to pull low the voltage of the first operation node and output terminal of the first and second output unit to the reference voltage according to the first, third, and fourth clock signals.

Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.