Abstract: A medical device (10) for use in a Magnetic Resonance environment includes a keypad (22) having keys (24). Light sources (26) are disposed with respective keys of the keypad to illuminate the respective keys. At least one electronic processor (18) is programmed to: perform user interfacing operations in which user inputs are received via the keypad; during the user interfacing operations, control the light sources to selectively illuminate keys usable in the user interfacing operations; and controlling or configuring the medical device in accord with the user inputs received during the user interfacing operations.

Abstract: An etching apparatus and an etching method thereof are provided. An end point detector detects a light intensity at a specific wavelength for light generated when an etching process is performed on a material to be processed, and generates an end point detection signal. The material to be processed includes a material layer and at least one mask layer formed on the material layer. A control device determines an etching completion time of the mask layer according to the end point detection signal, calculates a thickness of the mask layer according to the etching completion time, and adjusts an etching time of the material layer according to the thickness of the mask layer.

Abstract: An etching apparatus and an etching method thereof are provided. An end point detector detects a light intensity at a specific wavelength for light generated when an etching process is performed on a material to be processed, and generates an end point detection signal. The material to be processed includes a material layer and at least one mask layer formed on the material layer. A control device determines an etching completion time of the mask layer according to the end point detection signal, calculates a thickness of the mask layer according to the etching completion time, and adjusts an etching time of the material layer according to the thickness of the mask layer.

Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: The present disclosure provides a measurement method for a contact resistance of a transistor test device and a computer-readable medium. The measurement method includes: providing multiple transistor test devices, where the transistor test devices each include a source, a drain, an active layer, a gate located at the active layer, and wires connected to the source and the drain, widths of gates, channel region lengths of active layers, and quantities of connected wires of the transistor test devices are the same, and widths of the active layers of the transistor test devices are different; obtaining multiple total resistances of the transistor test devices by measuring the transistor test devices; and determining contact resistances of the transistor test devices based on the multiple total resistances and the widths of the active layers matching the total resistances.

Abstract: A chip packaging structure includes: at least one semiconductor chip, having a signal processing function; a base material, wherein the semiconductor chip is disposed on the base material; at least one thermal conduction plate, disposed on the base material; and a package material, encapsulating the base material, the thermal conduction plate, and the semiconductor chip. The thermal conduction plate forms at least one thermal conduction channel in the package material.

Abstract: A memory structure includes: a substrate including a memory array region and a peripheral circuit region; a plurality of bit line structures disposed in the memory array region of the substrate; a dummy bit line structure disposed on the substrate, wherein the dummy bit line structure is disposed in the memory array region and immediately adjacent to the peripheral circuit region; a plurality of contacts disposed between the bit line structures and in the memory array region; a dielectric layer disposed on the substrate and in the peripheral circuit region; and a protective structure disposed in the memory array region and immediately adjacent to the peripheral circuit region, wherein the protective structure includes the dummy bit line structure and a top surface of the protective structure is higher than top surfaces of the bit line structures.

Abstract: A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

Abstract: The present application provides a circuit and an associated chip. The circuit is coupled to a memory. The circuit includes: a first scan flip-flop (FF), being a previous-stage scan FF of an input terminal of the memory and having an output terminal coupled to an input terminal of the memory; and a second scan FF, being a next-stage scan FF of an output terminal of the memory and having an input terminal coupled to an output terminal of the memory; wherein a scan mode of the circuit has a load phase and a capture phase, during the capture phase, data output from the output terminal of the first scan FF loops back to a data input terminal of the first scan FF via a first loop, and the first loop is free from passing through the second scan FF.

Abstract: A method for forming a memory structure includes: providing a substrate including a memory array region and a peripheral circuit region; forming a plurality of bit line structures in the memory array region; forming a dielectric layer in the peripheral circuit region; forming a plurality of contacts between the bit line structures; depositing a protective layer on the substrate; depositing a hard mask layer on the protective layer; etching back the hard mask layer to form a hard mask spacer on the first top surface of the protective layer and immediately adjacent to the peripheral circuit region; and etching the protective layer with the hard mask spacer as an etching mask to leave a protective feature at the boundary between the memory array region and the peripheral circuit region.

Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

Abstract: A method for forming a memory structure includes: providing a substrate including a memory array region and a peripheral circuit region; forming a plurality of bit line structures in the memory array region; forming a dielectric layer in the peripheral circuit region; forming a plurality of contacts between the bit line structures; depositing a protective layer on the substrate; depositing a hard mask layer on the protective layer; etching back the hard mask layer to form a hard mask spacer on the first top surface of the protective layer and immediately adjacent to the peripheral circuit region; and etching the protective layer with the hard mask spacer as an etching mask to leave a protective feature at the boundary between the memory array region and the peripheral circuit region.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A dual membrane restrictor adapted to be connected to an oil supplying device, a loading device, and a recycling device is provided. The dual membrane restrictor includes a casing and first and second membranes. The casing has a first channel connected to the oil supplying device, first and second chambers, a second channel connected to the loading device, and a third channel connected to the recycling device. The first membrane is disposed in the first chamber divided into first upper and lower chambers by the first membrane. The first channel is connected to the first upper chamber. The second membrane is disposed in the second chamber divided into second upper and lower chambers by the second membrane. The second upper chamber is connected to the first lower chamber and the second channel. The second lower chamber is connected to the second channel and the third channel.

Abstract: A method for forming a semiconductor memory structure includes forming a hard mask layer over a semiconductor substrate, etching the hard mask layer to form first mask patterns and second mask patterns, transferring the first and second mask patterns to the substrate to form semiconductor blocks, and thinning down the second mask element. After thinning down the second mask element, the thickness of the second mask elements is less than the thickness of the first mask elements. The method also includes forming a first capping layer to laterally extend over the first mask patterns and the second mask patterns, and etching the first capping layer and the second mask pattern to form contact openings.

Abstract: A projection system and a projection image adjustment method thereof are provided. The projection image adjustment method is applicable to a processing device connected to multiple projectors, a display, and an input device, and includes the following steps. Arrangement information between the multiple projectors is obtained. Multiple adjustable areas corresponding to a projection image of each projector are simultaneously displayed on the display and the multiple adjustable areas are simultaneously displayed on projection images of the multiple projectors according to the arrangement information. A parameter setting interface corresponding to a first adjustable area among the multiple adjustable areas is displayed on the display. The first adjustable area corresponds to a first projector among the multiple projectors.

Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: A test system is provided that includes a memory test circuit, a memory, an input logic circuit, a bypass circuit, an output logic circuit and a register. The register is operated as a pipeline register of the memory test circuit and the output logic circuit. In a first test mode, the memory test circuit transmits a first test signal to the memory such that the memory outputs a memory output test signal to be stored in the register and further transmitted to the memory test circuit or the output logic circuit to perform test.

Abstract: A hydrostatic bearing assembly including a bearing and two membrane throttles is provided. The bearing is adapted to be movably disposed on a slide rail and includes two sub-bearing portions that are disposed opposite to each other on two opposite sides of the slide rail. The two membrane throttles are adapted to be connected to a pump. The pump is adapted to supply a fluid through the two membrane throttles to flow between the two sub-bearing portions and the slide rail, and each of the membrane throttles includes a casing and a throttling membrane piece. At least one of the casing and the corresponding sub-bearing portion includes a chamber, an inlet and an outlet communicating with the chamber, and an outlet surface, wherein the pump is adapted to be connected to the inlet, and the slide rail is adapted to be disposed adjacent to the outlet. The throttling membrane piece is being positioned in the chamber covers on the outlet surface.