Patents by Inventor Shih-Chung Chen

Shih-Chung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11618126
    Abstract: A polishing pad conditioning apparatus includes a base, a fiber, and a polymer protruding from a surface of the base and encompassing the fiber.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: April 4, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng, Hung-Lin Chen
  • Patent number: 11571782
    Abstract: The present disclosure provides a chemical mechanical polishing system having a unitary platen. The platen includes one or more recesses within the platen to house various components for the polishing/planarization process. In one embodiment, the platen includes a first recess and a second recess. The first recess is located under the second recess. An end point detector is placed in the first recess and a detector cover may be placed in the second recess. A sealing mean is provided in a space between the end point detector and the detector cover to prevent any external or foreign materials from coming in contact with the end point detector. A fastener used for fastening the detector cover to the platen also provides addition protection to prevent foreign materials from coming in contact with components received in the recesses.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Lung Lai, Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng, Rong-Long Hung
  • Publication number: 20230009839
    Abstract: A system and method for chemical mechanical polishing (“CMP”) pad replacement on a CMP processing tool. A platen carrier having two or more platens is positioned within a platen cleaning process module. Each platen includes a CMP pad affixed thereto, and is capable of being independently rotated during operations. When a pad requires replacement, the platen carrier rotates towards a pad tearer tool, which extends and pivots to remove the used pad from the platen as the carrier rotates. A pad tape replacement module is positioned above the CMP tool with pad tape extending from a supply roll to a recycle roll. As the pad tape transits through the module, a backing of the tape is separated and recycled. A pad disposed in the pad tape is then applied to a platen via a pressure roller.
    Type: Application
    Filed: January 20, 2022
    Publication date: January 12, 2023
    Inventors: Shih-Chung Chen, Wei-Kang Tu, Ching-Wen Cheng, Chun Yan Chen
  • Patent number: 11552082
    Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 10, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Sung-Kwan Kang, Gill Yong Lee, Sang Ho Yu, Shih Chung Chen, Jeffrey W. Anthis
  • Publication number: 20230005945
    Abstract: Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an ?-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).
    Type: Application
    Filed: September 9, 2022
    Publication date: January 5, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Jacqueline S. Wrench, Yixiong Yang, Yong Wu, Wei V. Tang, Srinivas Gandikota, Yongjing Lin, Karla M Bernal Ramos, Shih Chung Chen
  • Publication number: 20220367236
    Abstract: Some embodiments of the disclosure relate to methods of modifying a heater pedestal to improve temperature and thickness uniformity. Some embodiments of the disclosure relate to the modified heater pedestals with improved temperature and thickness uniformity. In some embodiments, the height of support mesas in different regions of the pedestal are modified to increase temperature uniformity. In some embodiments, the heater elements are moved above the vacuum channel and purge channel to increase temperature uniformity. In some embodiments, the edge ring is modified to be coplanar with the top of a supported substrate.
    Type: Application
    Filed: October 8, 2021
    Publication date: November 17, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Muhannad Mustafa, Yongjing Lin, Satish Radhakrishnan, Haoyan Sha, Shih Chung Chen, Mario D. Silvetti, Mandyam Sriram, Vijay D. Parkhe
  • Patent number: 11476267
    Abstract: Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an ?-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: October 18, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Jacqueline S. Wrench, Yixiong Yang, Yong Wu, Wei V. Tang, Srinivas Gandikota, Yongjing Lin, Karla M Bernal Ramos, Shih Chung Chen
  • Publication number: 20220165854
    Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-K dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAIN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAIC).
    Type: Application
    Filed: February 10, 2022
    Publication date: May 26, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Yongjing Lin, Karla M. Bernal Ramos, Shih Chung Chen, Yixiong Yang, Lin Dong, Steven C.H. Hung, Srinivas Gandikota
  • Publication number: 20220115516
    Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).
    Type: Application
    Filed: December 21, 2021
    Publication date: April 14, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Yongjing Lin, Karla M. Bernal Ramos, Luping Li, Shih Chung Chen, Jacqueline S. Wrench, Yixiong Yang, Steven C.H. Hung, Srinivas Gandikota, Naomi Yoshida, Lin Dong
  • Publication number: 20220098731
    Abstract: Methods of forming electronic devices comprising tungsten film stacks are provided. Methods include forming a tungsten nucleation layer on the barrier layer using an atomic layer deposition (ALD) process including a tungsten precursor that is free of fluorine. Forming the nucleation layer comprises controlling process parameters and/or forming WSi pre-nucleation layer.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Kedi Wu, Chenfei Shen, Chi-Chou Lin, Ilanit Fisher, Shih Chung Chen, Mandyam Sriram, Srinivas Gandikota
  • Patent number: 11289579
    Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), titanium oxide (TiO), tantalum oxide (TaO), and titanium aluminum carbide (TiAlC).
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: March 29, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Yongjing Lin, Karla M Bernal Ramos, Shih Chung Chen, Yixiong Yang, Lin Dong, Steven C. H. Hung, Srinivas Gandikota
  • Patent number: 11245022
    Abstract: Methods of forming and processing semiconductor devices are described. Certain embodiments related to electronic devices which comprise a dipole region having an interlayer dielectric, a high-? dielectric material, and a dipole layer. The dipole layer comprises one or more of titanium lanthanum nitride (TiLaN), titanium yttrium nitride (TiYN), titanium strontium nitride (TiSrN), titanium magnesium nitride (TiMgN, titanium aluminum nitride (TiAlN), titanium tantalum nitride (TiTaN), hafnium carbide (HfC), hafnium nitride (HfN), hafnium oxynitride (HfON), hafnium oxycarbide (HfOC), hafnium carbide aluminum (HfCAl), hafnium aluminum nitride (HfAlN), or hafnium carbonitride (HfCN).
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: February 8, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Yongjing Lin, Karla M. Bernal Ramos, Luping Li, Shih Chung Chen, Jacqueline S. Wrench, Yixiong Yang, Steven C. H. Hung, Srinivas Gandikota, Naomi Yoshida, Lin Dong
  • Publication number: 20210384036
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 9, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Chi-Chou Lin, Kedi Wu, Wen Ting Chen, Shih Chung Chen, Srinivas Gandikota, Mandyam Sriram, Chenfei Shen, Naomi Yoshida, He Ren
  • Publication number: 20210384035
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a fluorine-free metallic tungsten film. The fluorine-free metallic tungsten film is exposed to a second process condition to deposit a tungsten film on the fluorine-free metallic tungsten film.
    Type: Application
    Filed: April 8, 2021
    Publication date: December 9, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Shih Chung Chen, Kedi Wu, Ashley Lin, Chi-Chou Lin, Yi Xu, Yu Lei, Mandyam Sriram, Wen Ting Chen, Srinivas Gandikota, Chenfei Shen, Naomi Yoshida, He Ren
  • Patent number: 11171047
    Abstract: Methods of forming semiconductor device with fluorine-incorporated metal nitride films are described. A substrate surface is exposed to a metal fluoride precursor to form a metal-fluorine species on the substrate surface. The substrate surface is exposed to a nitriding agent to react with the metal-fluorine species to form a fluorine-incorporated metal nitride film.
    Type: Grant
    Filed: June 28, 2020
    Date of Patent: November 9, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yixiong Yang, Srinivas Gandikota, Steven C. H. Hung, Jacqueline S. Wrench, Yongjing Lin, Susmit Singha Roy, Wei V. Tang, Shih Chung Chen
  • Publication number: 20210288086
    Abstract: Methods and apparatus for forming reflector films are described A liner is formed on a substrate surface followed by formation of the reflector layer so that there is no oxygen exposure between liner and reflector layer formation. In some embodiments, a high aspect ratio structure is filled with a reflector material by partially filling the structure with the reflector material while growth is inhibited at a top portion of the structure, reactivating the top portion of the substrate and then filling the structure with the reflector material.
    Type: Application
    Filed: March 13, 2020
    Publication date: September 16, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Luping Li, Jacqueline S. Wrench, Wen Ting Chen, Yixiong Yang, In Seok Hwang, Shih Chung Chen, Srinivas Gandikota
  • Publication number: 20210268624
    Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.
    Type: Application
    Filed: May 12, 2021
    Publication date: September 2, 2021
    Inventors: Tsung-Lung Lia, Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng
  • Patent number: 11075276
    Abstract: Methods and apparatus for forming a semiconductor structure such as an NMOS gate electrode are described. Methods may include depositing a first capping layer having a first surface atop a first surface of a high-k dielectric layer; and depositing at least one metal layer having a first surface atop the first surface of the first capping layer, wherein the at least one metal layer includes titanium aluminum silicide material. Some methods include removing an oxide layer from the first surface of the first capping layer by contacting the first capping layer with metal chloride in an amount sufficient to remove an oxide layer. Some methods for depositing a titanium aluminum silicide material are performed by an atomic layer deposition process performed at a temperature of 350 to 400 degrees Celsius.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: July 27, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yongjing Lin, Shih Chung Chen, Naomi Yoshida, Lin Dong, Liqi Wu, Rongjun Wang, Steven Hung, Karla Bernal Ramos, Yixiong Yang, Wei Tang, Sang-Ho Yu
  • Patent number: 11062900
    Abstract: Methods and apparatus for forming a semiconductor structure with a scaled effective oxide thickness is disclosed. In embodiments, a method includes depositing amorphous silicon capping layer having a first surface atop a first surface of a titanium nitride (TiN) layer, wherein the titanium nitride layer is atop a first surface of a high-k dielectric layer disposed within a film stack; contacting the first surface of the amorphous silicon capping layer with a nitrogen containing gas; and annealing the film stack.
    Type: Grant
    Filed: December 1, 2019
    Date of Patent: July 13, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Luping Li, Shih Chung Chen, Kazuya Daito, Lin Dong, Zhebo Chen, Yixiong Yang, Steven Hung
  • Patent number: 11020837
    Abstract: In an embodiment, a chemical mechanical planarization (CMP) system includes: a monolithic platen within a platen housing, wherein the monolithic platen is formed of a single piece of material, wherein the monolithic platen includes: a first portion within a first opening, and a second portion within a second opening, wherein the first portion has a different diameter than the second portion; and a polishing fluid delivery module above the monolithic platen, wherein the polishing fluid delivery module is configured to deliver slurry to the monolithic platen during performance of CMP.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Lung Lai, Cheng-Ping Chen, Shih-Chung Chen, Sheng-Tai Peng