Patents by Inventor Shih-Hao Liu

Shih-Hao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10755320
    Abstract: A computer program product enables an advertisement audience dynamical detection circuit to conduct an advertisement audience quantity detecting operation. The advertisement audience quantity detecting operation includes: receiving a probe request frame transmitted from other wireless communication device; recording the arrival time of the probe request frame; inspecting the frame field configuration of the probe request frame; allocating the probe request to a corresponding data group according to the arrival time and frame field configuration of the probe request frame and a sequence control value in the header of the probe request frame while ensuring all probe request frames in the same data group have same frame field configuration; and calculating an estimated quantity of advertisement audiences passing through a specific location in a specific time period based on a total quantity of resulting data groups.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 25, 2020
    Assignee: AIRTAG TECHNOLOGY CO., LTD.
    Inventors: Shih-Hao Liu, Chang-Hung Ku, Shao-Chi Chang
  • Patent number: 10741926
    Abstract: A slot antenna structure for an electronic tag includes a dielectric layer, a conductor layer, a slot area and a capacitance adjustment unit. The electronic tag includes an identification chip. The conductor layer is disposed on the dielectric layer. The slot area is disposed in the conductor layer and includes an open slot, an open end and at least one closed slot. The open end is located at an edge of the conductor layer and extends inwardly to form the open slot for disposing the identification chip. The open slot has two sidewalls, and the two sidewalls have at least one turning point at a bottom portion of the open slot to form the closed slot. The capacitance adjustment unit is disposed on a surface of the dielectric layer different from the conductor layer to correspond to the slot area, thereby generating a capacitance effect.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 11, 2020
    Assignee: Compal Electronics, Inc.
    Inventors: Li-Chun Lee, Shih-Chia Liu, Yen-Hao Yu, Jhin-Ciang Chen, Chao-Lin Wu, Jui-Hung Lai
  • Publication number: 20200249397
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Inventors: Tao-Cheng LIU, Tsai-Hao HUNG, Shih-Chi KUO
  • Patent number: 10680120
    Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 9, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Ching-Yi Hsu, Shih-Hao Liu, Wu-Hsi Lu, Yun-Chou Wei, Chih-Cherng Liao
  • Publication number: 20200161764
    Abstract: A dual-band antenna is provided. The dual-band antenna includes a first antenna, a second antenna, and a grounding component. The first antenna has a first feed point for transceiving a first signal. The second antenna has a second feed point. The grounding component is electrically coupled to the first feed point and the second feed point, wherein the grounding component forms a first path and a second path between the first feed point and the second feed point, wherein a first path length of the first path and a second path length of the second path are integer multiples of a first wavelength of the first signal.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 21, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wen-Jiao Liao, Jhin-Ciang Chen, Shih-Chia Liu, Liang-Che Chou, Yen-Hao Yu, Li-Chun Lee
  • Patent number: 10641958
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tao-Cheng Liu, Tsai-Hao Hung, Shih-Chi Kuo
  • Publication number: 20200135653
    Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.
    Type: Application
    Filed: June 11, 2019
    Publication date: April 30, 2020
    Inventors: Po-Hao TSAI, Hsien-Wen LIU, Shin-Puu JENG, Meng-Liang LIN, Shih-Yung PENG, Shih-Ting HUNG
  • Patent number: 10629990
    Abstract: An antenna structure including a metal element, a first capacitor, a second capacitor, a feeding element and an adjustment element is provided. The metal element has an open slot, and the open slot has an open end, a first slot and a second slot. The first slot and the second slot are respectively disposed on two opposite sides of the open end. The feeding element crosses the first slot. A first end of the feeding element has a feeding point, and a second end of the feeding element is electrically connected to the metal element through the first capacitor. The adjustment element is disposed in the second slot. A first end of the adjustment element is electrically connected to the metal element, and a second end of the adjustment element is electrically connected to the metal element through the second capacitor.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 21, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Li-Chun Lee, Shih-Chia Liu, Yen-Hao Yu, Jhin-Ciang Chen, Chao-Lin Wu, Jui-Hung Lai
  • Patent number: 10572070
    Abstract: An optical device is provided. The optical device includes a substrate including a plurality of pixel units, a dielectric layer disposed on the substrate, a patterned light-transmitting layer disposed on the dielectric layer and corresponding to the plurality of pixel units, and a plurality of continuous light-shielding layers disposed on the dielectric layer and located on both sides of the patterned light-transmitting layer. A method for fabricating an optical device is also provided.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 25, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Cherng Liao, Shih-Hao Liu, Wu-Hsi Lu, Ming-Cheng Lo, Chung-Ren Lao, Yun-Chou Wei, Yin Chen, Hsin-Hui Lee, Hsueh-Jung Lin, Wen-Chih Lu, Ting-Jung Lu
  • Publication number: 20200057528
    Abstract: A touch module includes a touch panel unit, a conductive adhesive layer and a circuit board. The touch panel unit includes a substrate, a touch sensing structure disposed on the substrate, a signal transmitting structure disposed on the substrate and electrically connected to the touch sensing structure, and a protection layer covering a part of a surface of the signal transmitting structure. The protection layer and the substrate are disposed at two opposite sides of the signal transmitting structure. The conductive adhesive layer has a main portion which covers a region of the signal transmitting structure on which the protection layer is not disposed, and a cover portion which extends from the main portion and covers the protection layer. The circuit board is disposed on the conductive adhesive layer, and the circuit board and the signal transmitting structure are disposed at two opposite sides of the conductive adhesive layer.
    Type: Application
    Filed: August 15, 2019
    Publication date: February 20, 2020
    Inventors: Qi-Bin LIU, You-Zhi SHE, Kuo-Lung FANG, Jun-Rong CHEN, Shih-Hao CHEN, Jun-Ping YANG, Xiao-Xia YOU, Qi-Jun ZHENG, Jun-Jie ZHENG
  • Publication number: 20200006085
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Application
    Filed: April 12, 2019
    Publication date: January 2, 2020
    Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
  • Publication number: 20190391701
    Abstract: An optical device is provided. The optical device includes a substrate including a plurality of pixel units, a dielectric layer disposed on the substrate, a patterned light-transmitting layer disposed on the dielectric layer and corresponding to the plurality of pixel units, and a plurality of continuous light-shielding layers disposed on the dielectric layer and located on both sides of the patterned light-transmitting layer. A method for fabricating an optical device is also provided.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng LIAO, Shih-Hao LIU, Wu-Hsi LU, Ming-Cheng LO, Chung-Ren LAO, Yun-Chou WEI, Yin CHEN, Hsin-Hui LEE, Hsueh-Jung LIN, Wen-Chih LU, Ting-Jung LU
  • Patent number: 10508020
    Abstract: The present disclosure provides a substrate structure for a micro electro mechanical system (MEMS) device. The substrate structure includes a cap and a micro electro mechanical system (MEMS) substrate. The cap has a cavity, and the MEMS substrate is disposed on the cap. The MEMS substrate has a plurality of through holes exposing the cavity, and an aspect ratio of the through hole is greater than 30.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsai-Hao Hung, Shih-Chi Kuo, Tsung-Hsien Lee, Tao-Cheng Liu
  • Publication number: 20190369499
    Abstract: Embodiments herein beneficially enable simultaneous processing of a plurality of substrates in a digital direct write lithography processing system. In one embodiment a method of processing a plurality of substrate includes positioning a plurality of substrates on a substrate carrier of a processing system, positioning the substrate carrier under the plurality of optical modules, independently leveling each of the plurality of substrates, determining offset information for each of the plurality of substrates, generating patterning instructions based on the offset information for each of the plurality of substrates, and patterning each of the plurality of substrates using the plurality of optical modules. The processing system comprises a base, a motion stage disposed on the base, the substrate carrier disposed on the motion stage, a bridge disposed above a surface of the base and separated therefrom, and a plurality of optical modules disposed on the bridge.
    Type: Application
    Filed: March 19, 2019
    Publication date: December 5, 2019
    Inventors: Chien-Hua LAI, Chia-Hung KAO, Hsiu-Jen WANG, Shih-Hao KUO, Yi-Sheng LIU, Shih-Hsien LEE, Ching-Chang CHEN, Tsu-Hui YANG
  • Publication number: 20190348762
    Abstract: An antenna apparatus and an electronic apparatus are provided. The electronic apparatus includes the antenna apparatus. The antenna apparatus includes a radiator, a first and a second impedance control circuit. The radiator receives and transmits a radio frequency (RF) signal. The first impedance control circuit is electrically connected to the radiator and transmits the RF signal. The second impedance control circuit includes an impedance matching circuit and an inductor. The first end of the impedance matching circuit is electrically connected to the radiator. The impedance matching circuit adjusts the impedance matching of the radiator and transmits a sensing signal. The inductor is electrically connected to the second end of the impedance matching circuit. The inductor transmits a sensing signal, and blocks the RF signal. Accordingly, the structures of the antenna and the circuit can be simplified, and the influence between the RF signal and the sensing signal can be reduced.
    Type: Application
    Filed: May 13, 2019
    Publication date: November 14, 2019
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: An-Yao Chou, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Jhin-Ciang Chen, Chao-Lin Wu, Jui-Hung Lai
  • Publication number: 20190341322
    Abstract: A semiconductor package includes an encapsulated semiconductor device, a redistribution structure, and a protection layer. The encapsulated semiconductor device includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. The redistribution structure is disposed on the encapsulated semiconductor device and includes a dielectric layer and a redistribution circuit layer electrically connected to the semiconductor device. The protection layer at least covers the dielectric layer, wherein an oxygen permeability or a water vapor permeability of the protection layer is substantially lower than an oxygen permeability or a vapor permeability of the dielectric layer.
    Type: Application
    Filed: July 22, 2019
    Publication date: November 7, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Hao Tseng, Hung-Jui Kuo, Ming-Che Ho, Chia-Hung Liu
  • Patent number: 10459341
    Abstract: Embodiments of the present disclosure generally provide a digital lithography system that can process both large area substrates as well as semiconductor device substrates, such as wafers. Both the large area substrates and the semiconductor device substrates can be processed in the same system simultaneously. Additionally, the system can accommodate different levels of exposure for forming the features over the substrates. For example, the system can accommodate very precise feature patterning as well as less precise feature patterning. The different exposures can occur in the same chamber simultaneously. Thus, the system is capable of processing both semiconductor device substrates and large area substrates simultaneously while also accommodating very precise feature patterning simultaneous with less precise feature patterning.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: October 29, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chien-Hua Lai, Ching-Chang Chen, Shih-Hao Kuo, Tsu-Hui Yang, Hsiu-Jen Wang, Yi-Sheng Liu, Chia-Hung Kao
  • Patent number: 10454167
    Abstract: An antenna structure includes a substrate, a metal element, and a feeding element. The metal element has an open slot. The open slot forms a first resonant path. The substrate is disposed on the metal element. The feeding element is disposed on the substrate, and the metal element and the feeding element are respectively disposed on two opposite sides of the substrate. The feeding element includes a feeding end and a shorting end electrically connected to the metal element. An orthogonal projection of the feeding element on the metal element is partially overlapped with the open slot. The feeding element forms a second resonant path extending from the feeding end to the shorting end. The antenna structure operates in a first band through the first resonant path and operates in a second band through the second resonant path.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 22, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yen-Hao Yu, Li-Chun Lee, Jui-Hung Lai, Shih-Chia Liu, Jhin-Ciang Chen, Chao-Lin Wu
  • Publication number: 20190312154
    Abstract: A semiconductor device includes a substrate, a well region formed in the substrate, first and second isolation regions formed in the substrate, a dielectric layer formed on the well region, a conductive layer formed on the dielectric layer, a first doped region, an insulating layer, and first and second contact vias. The dielectric layer is disposed between the first and second isolation regions. The first doped region is formed in the well region. The insulating layer is formed on the dielectric layer, the first and second isolation regions, and the first doped region. The first contact via is formed in the insulating layer and electrically connected to the conductive layer. The first contact via is disposed on an overlapping area between the dielectric layer and the conductive layer. The second contact via is formed in the insulating layer and electrically connected to the doped region.
    Type: Application
    Filed: April 5, 2018
    Publication date: October 10, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Ching-Yi HSU, Shih-Hao LIU, Wu-Hsi LU, Yun-Chou WEI, Chih-Cherng LIAO
  • Publication number: 20190293867
    Abstract: A method includes: forming a first plurality of tiers that each comprises first and second dummy layers over a substrate, wherein within each tier, the second dummy layer is disposed above the first dummy layer; forming a second plurality of recessed regions in the first plurality of tiers, wherein at least one subgroup of the second plurality of recessed regions extend through respective different numbers of the second dummy layers; and performing an etching operation to concurrently forming a third plurality of trenches with respective different depths in the substrate through the at least one subgroup of the second plurality of recessed regions.
    Type: Application
    Filed: April 8, 2019
    Publication date: September 26, 2019
    Inventors: Tao-Cheng LIU, Tsai-Hao Hung, Shih-Chi Kuo