Abstract: A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time.

Abstract: A computer system including a chassis, a plurality of motherboards, a fan control module and a plurality of fans is provided. A plurality of motherboard position signal generating units is disposed in the chassis. Each of the motherboards includes a signal generating circuit and a board management controller. The signal generating circuit coordinates with one of the motherboard position signal generating units to generate a motherboard position signal. The board management controller receives the motherboard position signal and a motherboard working temperature signal to output a motherboard working state signal. The fan control module coupled to the board management controller of each of the motherboards receives the motherboard working state signals and generates a plurality of fan control signals accordingly. The fans coupled to the fan control module determine operation according the fan control signals.

Abstract: A power factor correction circuit including a boost converter, a first capacitor, a first resistor, and a boost control unit is provided. The boost control unit includes a signal generator and a frequency controller. The boost converter transforms a rectified voltage to a correction voltage according to a pulse width modulation (PWM) signal. The first capacitor and the first resistor are coupled between an input terminal and a ground terminal of the boost converter. The boost control unit is adapted to generate the PWM signal, and adjust a duty cycle and a frequency of the PWM signal according to a current flowing through the first resistance, the rectified voltage and the correction voltage. Wherein, the signal generator is adapted to generate a ramp signal and adjust a slope of the ramp signal according to a charging current. The frequency controller adjusts the charging current according to the rectified voltage.

Abstract: A computer system including a power supply and N main boards is provided, herein N is an integer greater than 1. The power supply generates a main power and a standby power. The N main boards respectively correspond to one standby voltage. The 1st to the (N-1)th main boards respectively generate the corresponding standby voltage by the main power in a power-on state, and respectively generate the corresponding standby voltage by the standby power in a power-off state. The Nth main board generates the corresponding standby voltage by the main power in the power-on and power-off state.

Abstract: A computer system including a first and second main boards, a judgment unit, a power supply, a first switch and second switch is provided. The judgment unit receives a first and second power start signals from the first and second main boards, and outputs a total power start signal. The power supply outputs a power reply signal according to the total power start signal. The first and second switches determine whether to output a power good signal individually according to the first and second power start signals. When one of the first and second power start signals is available, the total power start signal and the power reply signal are available, and the power supply outputs an operating voltage. When the first and second power start signals are unavailable, the total power start signal and the power reply signal are unavailable, and the power supply stops outputting the operating voltage.

Abstract: A computer capable of automatic bandwidth configuration according to I/O expansion card (e.g., PCI-Express expansion card) type is provided. A motherboard of the computer includes an I/O expansion slot, a chipset, and a configuration setting circuit. When the I/O expansion slot supports different types of I/O expansion cards having multiple interface card slot combinations, a corresponding bandwidth configuration message is generated on the I/O expansion card. The bandwidth configuration message is used to indicate the type of the I/O expansion card that is being used and thereby control the configuration setting circuit to adjust the bandwidth configuration in the chipset.

Abstract: A computer start-up timing control device and a method thereof are provided for generating a power supply signal to enable a power supply unit (PSU) to provide power. The device includes a chipset, a delay circuit, and a logic gate. The delay circuit delays a standby power ready signal of the computer to generate a standby power delay signal. The chipset generates a power supply signal. The standby power delay signal enables the logic gate to transmit the power supply signal to the PSU via the logic gate. The PSU provides a power to make the computer enter a start-up procedure. The standby power delay signal delays the time for the chipset to send a power supply signal, so that a baseboard management controller (BMC) has enough time to complete initialization. Therefore, the chipset is prevented from accessing the BMC and obtaining erroneous information before the BMC finishes initialization.

Abstract: A method for treating presences is performed as follows. A watcher uses “subscribe” in requesting to subscribe presences of contact persons, and the updated presences of the contact persons are transmitted by “notify” to the watchers through a filtering scheme. The filtering scheme is based on GUI display of the watchers, the last accessing time of the contact persons, and/or the auto leave status of the watcher.

Abstract: A power discharge control system for eliminating residual voltage of electronic components in an electronic device, is proposed, which includes a control IC for outputting first electrical signals of a first level and a second level respectively corresponding to power on and power off of the electronic device; a power supply for receiving the first electrical signal, and providing or terminating operation power to the electronic component accordingly, and delaying outputting of a second electrical signal equivalent to the first electrical signal level; a logic judgment module connected to the control IC and the power supply for receiving the first and the second electrical signals for executing logic operation process, when at least one of the first and the second electrical signals is at the first level, a third electrical signal of a third level is outputted, when both the first and the second electrical signals are at the second level, a third electrical signal of a fourth level is outputted; and at least

Abstract: A fan speed control device includes a management selection module, a first and a second buffers, a resistor, a transistor, and a switch. Depending upon whether a motherboard supports a system of a baseboard management control or not, the fan speed control device selectively uses an indicative signal of a serial input and output interface or an indicative signal of the baseboard management control to indicate a power-on status. At the power-on moment, the fan speed control device controls the fan to operate at its minimum speed, so that a system crash due to a power output shortage of a power supply can be avoided. As the system enters stable operation, the fan speed is controlled by a pulse width modulation signal.

Abstract: A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories.

Abstract: A power factor correction circuit including a boost converter, a first capacitor, a first resistor, and a boost control unit is provided. The boost control unit includes a signal generator and a frequency controller. The boost converter transforms a rectified voltage to a correction voltage according to a pulse width modulation (PWM) signal. The first capacitor and the first resistor are coupled between an input terminal and a ground terminal of the boost converter. The boost control unit is adapted to generate the PWM signal, and adjust a duty cycle and a frequency of the PWM signal according to a current flowing through the first resistance, the rectified voltage and the correction voltage. Wherein, the signal generator is adapted to generate a ramp signal and adjust a slope of the ramp signal according to a charging current. The frequency controller adjusts the charging current according to the rectified voltage.

Abstract: A power supply and a bootstrap circuit thereof are provided. The bootstrap circuit includes a transistor, a first capacitor, a first impedance and a regulator circuit. The collector and the emitter of the transistor respectively serve as the input terminal and the output terminal of the bootstrap circuit. A terminal of the first capacitor is coupled to the collector of the transistor. A terminal of the first impedance is coupled to another terminal of the first capacitor. The regulator circuit is coupled to another terminal of the first impedance and the base of the transistor for clamping the voltage of the above-mentioned base at a predetermined voltage level.

Abstract: An apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address is provided. The apparatus is composed by all cheap electronic devices, so as to achieve a purpose of lowering a cost for design. In addition, in the apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address of the invention, all the I2C slave devices are addressed by an I2C master device to perform the data transmission subsequently before a basic input/output system (BIOS) completes a power-on self-test (POST), but all the I2C slave devices are addressed by a system chip (for example, a baseboard management controller (BMC)) to perform the data transmission subsequently after the BIOS completes the POST. Therefore, the purpose of performing the data transmission for all the I2C slave devices on real time is achieved.

Abstract: An apparatus for automatically regulating a system ID of a motherboard of a server and a server having the same are provided. Under a condition that when a rack server is applied to different server systems, the rack server requires different riser cards, while a tower server does not require any riser card, whenever a corresponding riser card or a device card is inserted into the slot of the motherboard of the server, the present invention can automatically regulate a system ID of a motherboard of a server by designing the motherboard of the server compatible with a plurality of server systems as retained at a same status, i.e., retaining the any status configured on the motherboard unchanged.

Abstract: An apparatus and a method for identifying a system style are provided. The apparatus includes a motherboard and a peripheral backplane. The motherboard is suitable for assembling other backplanes. The peripheral backplane is coupled to the motherboard not only through a signal-data interface but also through an inter-integrated circuit (I2C) bus or a system management (SM) bus. The method includes following steps. First, an identification information is stored on the peripheral backplane. Next, the motherboard reads the identification information from the peripheral backplane through the I2C bus or the SM bus. The motherboard then identifies the system style according to the identification information and is then configured accordingly. Thereby, the motherboard needs not to be configured manually and can be directly applied in different chassis systems supported by the motherboard.

Abstract: A power supply device is provided according to the present invention. The power supply device is applicable to electronic device, which has a non-volatile memory and a power supply circuit that provides power to the non-volatile memory. The power supply device includes: a power consuming unit for providing the non-volatile memory with a power release path; a control unit electrically connected to the power supply circuit, the non-volatile memory, and the power consuming unit, has and having a first connection end, a switching end, and a second connection end for being selectively electrically connected to the first connection end or the second connection end via the switching end.

Abstract: A storage device backplane and an identification circuit for identifying using situations of the storage device backplane are provided. The storage device backplane possesses a first connection interface and a second connection interface, for being used as a first backplane supporting a motherboard, or a second backplane cascaded to the first backplane, or a first backplane supporting a daughterboard of the motherboard. The first and second backplanes possess the same storage device backplane structure. If the storage device backplane is used as the first backplane, a first connection interface of the first backplane is coupled to the motherboard or the daughterboard thereof; if the storage device backplane is used as the second backplane, a first connection interface of the second backplane is coupled to a second connection interface of the first backplane. The identification circuit identifies using situations of the storage device backplane and display corresponding correct indicator number.

Abstract: A linear step-down voltage regulator is provided. The linear step-down voltage regulator is grounded with a ground terminal. The ground terminal is electrically connected to a digital ground terminal of a switching circuit. The linear step-down voltage regulator includes a pass element, a voltage dividing resistor, an error amplifier, a metal oxide semiconductor (MOS) transistor, and a low-pass filter. The employment of the low-pass filter effectively adjusts and restricts the switching noise to pass therethrough, so as to decrease the output of the switching noise and thus eliminating the problems due to the noise.

Abstract: A voltage regulating circuit including an error signal generator, a comparator, a switch unit, a low-pass filter and a modulating unit is provided. The error signal generator respectively receives a reference voltage signal and a feedback signal, and generates an error signal. The comparator respectively receives the error signal and a comparing signal, and generates a pulse width modulation signal. The switch unit regulates an input voltage signal to generate an output voltage signal according the pulse width modulation signal. The low-pass filter filters out the high frequency of the output signal and produces the feedback signal. The modulating unit is coupled to the low-pass filter and the error signal generator for regulating a transient voltage of the output voltage signal.