Abstract: A device includes gate spacers over a substrate, and a gate structure between the gate spacers. The gate structure includes an interfacial layer over the substrate, a metal oxide layer over the interfacial layer, a metal oxide layer over the interfacial layer, a first metal nitride layer over the metal oxide layer, a second metal nitride over the first metal nitride layer, and a tungsten-containing material interposing the first metal nitride layer and the second metal nitride layer.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming an interlayer dielectric structure over the source/drain epitaxial structures. The method also includes etching the interlayer dielectric structure to form an opening exposing the source/drain epitaxial structures. The method also includes depositing a first spacer layer over sidewalls of the interlayer dielectric structure in the opening. The method also includes forming a silicide structure over the source/drain epitaxial structures. The method also includes forming a bottom contact structure over the silicide structure. The method also includes depositing a second spacer layer over the first spacer layer.

Abstract: A semiconductor device includes a plurality of active components and an isolation component. Each active component includes a plurality of active channel sheets vertically stacked and a metal gate. The isolation component isolates the adjacent two of the active components, and includes a plug structure. The plug structure is formed of a material the same as that of the metal gate.

Abstract: Methods for forming a gate structure of a multi-gate device are provided. An example method includes depositing a gate dielectric layer over first nanostructures over a first region of a substrate and second nanostructures over a second region of the substrate, depositing a first work function metal (WFM) layer over the first nanostructures and the second nanostructures, depositing a first hard mask (HM) layer over the first WFM layer, selectively removing the first HM layer and the first WFM layer over the first region, selectively removing the first HM layer over the second region, depositing a second WFM layer over the substrate, depositing a second HM layer over the second WFM layer, selectively removing the second HM layer and the second WFM layer over the first region, selectively removing the second HM layer over the second region, and depositing a third WFM layer over the substrate.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a source/drain feature over an active region, forming a gate stack across the active region, forming an interlayer dielectric layer over the source/drain feature, and etching the interlayer dielectric layer to form an opening exposing the source/drain feature. The opening has a first sidewall extending in a first horizontal direction and a second sidewall extending in a second horizontal direction. The method also includes forming a contact liner along the opening, and forming a contact plug in the opening. A first portion of the contact liner along the first sidewall of the opening is thinner than a second portion of the contact liner along the second sidewall of the opening.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes first and second gate spacers formed over a semiconductor substrate, longitudinally extending along a first direction, and separated from each other by a gate electrode layer. A first insulating layer longitudinally extends along a second direction to pass through the gate electrode layer and the first and second gate spacers. A gate dielectric layer has a top surface covered by the gate electrode layer. The top width of the gate dielectric layer is less than that of the gate electrode layer. The first and second gate spacers and the first insulating layer have first, second and third hydrophobic surfaces, respectively. These hydrophobic surfaces are in direct contact with first, second and third sidewall surfaces of the gate electrode layer, respectively.

Abstract: A cavity-backed slot antenna system provided in this disclosure is installed in a housing of an electronic device and includes a metal cavity, a supporting element, an antenna device, a conductive post, and a coupling metal part. The metal cavity is in the housing and includes an opening and a closed surface opposite to each other. A slot is on the closed surface. The supporting element is in the metal cavity. The antenna device is in the metal cavity and on the supporting element, to expose one side surface of the antenna device. The antenna device includes a feed source. The conductive post penetrates the antenna device and connects to the metal cavity. The coupling metal part is in the housing and close to the opening of the metal cavity, so that the coupling metal part is close to and corresponds to the feed source of the antenna device.

Abstract: A method for forming a semiconductor device structure includes forming nanostructures over a substrate. The method also includes forming a gate structure wrapped around the nanostructures. The method also includes forming source/drain epitaxial structures over opposite sides of the nanostructures. The method also includes forming a first interlayer dielectric structure over the source/drain epitaxial structures. The method also includes removing the first interlayer dielectric structure. The method also includes forming a recess in the source/drain epitaxial structures. The method also includes forming a silicide structure in the recess. The method also includes forming a second interlayer dielectric structure over the silicide structure.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate having a base and a fin over the base. The method includes forming a first gate stack wrapped around the fin. The method includes forming a first gate spacer over a first sidewall of the first gate stack. The method includes partially removing the fin, which is not covered by the first gate stack and the first gate spacer. The method includes removing a first upper portion of the first gate stack to expose a second upper portion of the first gate spacer. The method includes removing the second upper portion of the first gate spacer. The method includes removing a first lower portion of the first gate stack and the fin originally wrapped by the first gate stack. The method includes forming a dielectric channel-cut structure in the trench.

Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

Abstract: A semiconductor device includes a semiconductor substrate, a plurality of metal portions, a plurality of nanosheet structures, and a plurality of isolation structures. The metal portions are disposed on the semiconductor substrate and are spaced apart from each other. The nanosheet structures are surrounded by the metal portions such that the nanosheet structures are spaced apart from each other. The isolation structures are disposed on the semiconductor substrate such that two adjacent ones of the metal portions are isolated from each other by a corresponding one of the isolation structures. Each of the isolation structures includes a first dielectric layer and an air gap surrounded by the first dielectric layer.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes semiconductor nanosheets vertically stacked upon one another and disposed above a semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, and source/drain regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions, and a topmost semiconductor nanosheet most distanced from the semiconductor substrate is thinner than an underlying semiconductor nanosheet between the topmost semiconductor nanosheet and the semiconductor substrate.

Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first active region, forming an interlayer dielectric layer over a source/drain region of the first active region, forming a gate stack to surround the channel region of the first active region, and etching the gate stack and the interlayer dielectric layer to form a cutting trench. The cutting trench includes a first portion extending into the gate stack and a second portion extending into the interlayer dielectric layer. A first width of the first portion of the cutting trench is different than a second width of the second portion of the cutting trench in a direction parallel to a longitudinal axis of the gate stack. The method also includes forming a gate cutting structure in the cutting trench.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a first interlayer dielectric layer surrounding a first portion of the source/drain region, a second interlayer dielectric layer distinct from the first interlayer dielectric layer surrounding a second portion of the source/drain region, a silicide layer disposed on the source/drain region, and a conductive contact disposed over the source/drain region. The conductive contact is disposed in the second interlayer dielectric layer.

Abstract: A semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate. The structure also includes gate structures that are wrapped around the first nanostructures and the second nanostructures and that extend along a first direction. The structure also includes a dielectric structure formed between two of the gate structures and parallel to the gate structures. A first sidewall of the first nanostructures is shifted from a first sidewall of the second nanostructures in a second direction, the second direction is different from the first direction.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.

Abstract: A semiconductor device includes a plurality of nanostructures over a substrate arranged in a z-axis and a gate stack wrapping around the plurality of nanostructures. Thea gate stack comprises a gate dielectric layer and a p-type work function material on the gate dielectric layer. The gate dielectric layer wraps around the plurality of nanostructures. The p-type work function material has a first thickness along the z-axis above a topmost one of the plurality of nanostructures and a second thickness along the z-axis between neighboring two of the plurality of nanostructures, and the first thickness is less than the second thickness.

Abstract: An electronic device co-constructed with a hinge antenna and the hinge antenna thereof are provided. The electronic device includes a first casing, a second casing, a hinge assembly, and a hinge antenna. The hinge assembly is connected to the first casing and the second casing, so that the first casing and the second casing are opened and closed through rotation of the hinge assembly. The hinge assembly includes a horizontal fixed shaft. The hinge antenna is mounted on the horizontal fixed shaft and fixed on the hinge assembly. Therefore, the hinge antenna is mounted on the hinge assembly on the premise of maintaining the original appearance design, to improve the space utilization of the antenna.

Abstract: A device includes gate spacers over a substrate, and a gate structure between the gate spacers. The gate structure includes an interfacial layer over the substrate, a metal oxide layer over the interfacial layer, a metal oxide layer over the interfacial layer, a first metal nitride layer over the metal oxide layer, a second metal nitride over the first metal nitride layer, and a tungsten-containing material interposing the first metal nitride layer and the second metal nitride layer.