Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming an isolation feature over a semiconductor substrate. The semiconductor substrate includes a fin structure over the isolation feature. Two opposing spacer elements are formed over the isolation feature and across the fin structure so as to define a gate opening. The gate opening exposes the fin structure and the isolation feature and inner sidewalls of the gate opening have carbon-containing hydrophobic surfaces. A gate structure is formed in the gate opening with the carbon-containing hydrophobic surfaces.

Abstract: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

Abstract: A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having width a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.

Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.

Abstract: A method is provided. The method includes the following operations. A dielectric layer is deposited over a substrate. Then, a first work function metal layer is deposited over the dielectric layer. Next, a dummy layer is deposited over the first work function metal layer. Afterwards, an impurity is introduced into the first work function metal layer. Then, the dummy layer is etched. Next, a second work function metal layer is deposited over the first work function metal layer.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

Abstract: A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

Abstract: A method of manufacturing a semiconductor Fin FET includes forming a fin structure over a substrate. The fin structure includes an upper layer, part of which is exposed from an isolation insulating layer. A dummy gate structure is formed over part of the fin structure. The dummy gate structure includes a dummy gate electrode layer and a dummy gate dielectric layer. A source and a drain are formed. The dummy gate electrode is removed so that the upper layer covered by the dummy gate dielectric layer is exposed. The upper layer of the fin structure is removed to make a recess formed by the dummy gate dielectric layer. Part of the upper layer remains at a bottom of the recess. A channel layer is formed in the recess. The dummy gate dielectric layer is removed. A gate structure is formed over the channel layer.

Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.

Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.

Abstract: A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.

Abstract: An NMOS transistor gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region and lining an inner sidewall of the spacer, a bottom barrier layer conformally disposed on the gate dielectric layer, a work function metal layer disposed on the bottom barrier layer, and a filling metal partially wrapped by the work function metal layer. The bottom barrier layer has an oxygen concentration higher than a nitrogen concentration. The bottom barrier layer is in direct contact with the gate dielectric layer. The bottom barrier layer includes a material selected from Ta, TaN, TaTi, TaTiN and a combination thereof.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.

Abstract: A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

Abstract: A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent.