Patents by Inventor Shih-Kuang Chiu

Shih-Kuang Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10950507
    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 16, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Patent number: 10772390
    Abstract: A buckle device comprises a main unit, a disk unit, a press unit, and an elastic unit. The main unit includes a housing. The disk unit includes at least one vertical disk. The press unit includes a press body. The elastic unit includes a first spring body. One end of the first spring body is disposed on the vertical disk. The other end of the first spring body is disposed on the press body. The first spring body is a thrust spring to extend the lifespan of the buckle device.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: September 15, 2020
    Assignee: BROGENT TECHNOLOGIES INC.
    Inventors: Shih-Kuang Chiu, Po-Tsun Chen, Juei-Tsung Chen
  • Publication number: 20200221830
    Abstract: A buckle device comprises a main unit, a disk unit, a press unit, and an elastic unit. The main unit includes a housing. The disk unit includes at least one vertical disk. The press unit includes a press body. The elastic unit includes a first spring body. One end of the first spring body is disposed on the vertical disk. The other end of the first spring body is disposed on the press body. The first spring body is a thrust spring to extend the lifespan of the buckle device.
    Type: Application
    Filed: October 16, 2019
    Publication date: July 16, 2020
    Inventors: Shih-Kuang CHIU, Po-Tsun CHEN, Juei-Tsung CHEN
  • Patent number: 10615055
    Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: April 7, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
  • Publication number: 20190246988
    Abstract: A physiological signal correction device, a correction method, and a wearable device with a correction function are provided. The physiological signal correction device includes a physiological signal sensor, a warping sensor, and a signal processing device. The physiological signal sensor is attached to an object to be detected to obtain a physiological signal value from at least one sensing electrode. The warping sensor is disposed on the physiological signal sensor and detects whether a warping condition of the physiological signal sensor with respect to the object to be detected occurs. The signal processing device corrects the physiological signal value provided by the physiological signal sensor according to the warping condition. The warping condition is caused by a distance between a part of the sensing electrode and the object to be detected or a change in a contact area between a part of the sensing electrode and the object to be detected.
    Type: Application
    Filed: January 31, 2019
    Publication date: August 15, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Huan Yang, Cheng-Chung Lee, Shih-Kuang Chiu, Kuang-Ching Fan
  • Publication number: 20190122898
    Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
  • Publication number: 20190103360
    Abstract: A flexible chip package is provided. The flexible chip package includes a first flexible substrate; a first redistribution layer disposed on the first flexible substrate; a second flexible substrate; a second redistribution layer disposed on the second flexible substrate; a semiconductor chip disposed between the first and second redistribution layers and electrically connected to at least one of the first and second redistribution layers; and a first bonding layer disposed between the first and second redistribution layers and encapsulating the semiconductor chip, wherein the first bonding layer, the first redistribution layer and the second redistribution layer are between the first flexible substrate and the second flexible substrate.
    Type: Application
    Filed: March 13, 2018
    Publication date: April 4, 2019
    Applicants: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Cheng-Hung Yu, Tai-Jui Wang, Chieh-Wei Feng, Shih-Kuang Chiu, Ming-Huan Yang
  • Patent number: 10199239
    Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
  • Publication number: 20180254227
    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
    Type: Application
    Filed: May 7, 2018
    Publication date: September 6, 2018
    Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Patent number: 10049955
    Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: August 14, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
  • Patent number: 9991178
    Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: June 5, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
  • Publication number: 20180125172
    Abstract: A latch device comprises a housing unit, a disk unit, an electromagnetic lock unit, a pressing lock unit, and a detecting unit. The housing unit includes a housing, which has a pressing hole and an insertion slot. The disk unit includes a supporting rod positioned through the housing, and two vertical disks pivotally arranged to the supporting rod. The outer perimeter of the two disks is placed with a hook, a first engaging portion and a second engaging portion. The electromagnetic lock unit includes two electromagnetic mechanisms, two retractable bars connected to the two electromagnetic mechanisms, and two electromagnetic latches respectively connected to the two retractable bars. The pressing lock unit includes a pushbutton, and a button latch connected to the pushbutton. The detecting unit includes two detectors, which are disposed inside the housing for detecting the position of the two electromagnetic latches.
    Type: Application
    Filed: October 19, 2017
    Publication date: May 10, 2018
    Inventors: Ke-Cheng Chien, Wei-Ching Tang, Chih-Chiang Huang, Guo-Sen Lian, Shih-Kuang Chiu
  • Patent number: 9899237
    Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
  • Patent number: 9899308
    Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: February 20, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
  • Patent number: 9875981
    Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: January 23, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
  • Patent number: 9812340
    Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 7, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
  • Publication number: 20170229387
    Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 10, 2017
    Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
  • Publication number: 20170229364
    Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.
    Type: Application
    Filed: April 26, 2017
    Publication date: August 10, 2017
    Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
  • Publication number: 20170148761
    Abstract: The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor element having opposing active and non-active surfaces, and side surfaces abutting the active surface and the non-active surface; applying an adhesive material in the groove and around a periphery of the side surfaces of the semiconductor element; forming a dielectric layer on the adhesive material and the active surface of the semiconductor element; forming on the dielectric layer a circuit layer electrically connected to the semiconductor element; and removing a first portion of the carrier below the groove to keep a second portion of the carrier on a side wall of the groove intact for the second portion to function as a supporting member. The present invention does not require formation of a silicon interposer, and therefore the overall cost of a final product is much reduced.
    Type: Application
    Filed: January 6, 2017
    Publication date: May 25, 2017
    Inventors: Guang-Hwa Ma, Shih-Kuang Chiu, Shih-Ching Chen, Chun-Chi Ke, Chang-Lun Lu, Chun-Hung Lu, Hsien-Wen Chen, Chun-Tang Lin, Yi-Che Lai, Chi-Hsin Chiu, Wen-Tsung Tseng, Tsung-Te Yuan, Lu-Yi Chen, Mao-Hua Yeh
  • Patent number: 9659806
    Abstract: A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: May 23, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Hong-Da Chang, Shih-Kuang Chiu