Patents by Inventor Shih-Kuang Chiu
Shih-Kuang Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11751642Abstract: A buckle device capable of displaying a locked state includes a main body unit, a latch unit, a fastening unit, an electromagnetic unit, and a control unit. The main body unit includes a main body and the latch unit includes a detachable tongue element. The fastening unit includes a bolt body interfering with the tongue element. The electromagnetic unit includes an electromagnetic module and an electromagnetic rod. The electromagnetic module controls the electromagnetic rod to interfere with the bolt body. The control unit includes a control module, a display module and a magnetic rod detection module for detecting the position of the electromagnetic rod. The control unit receives detection information of the magnetic bolt detection module and controls the display module to display a current state according to the position of the at least one electromagnetic rod.Type: GrantFiled: August 17, 2022Date of Patent: September 12, 2023Assignee: BROGENT TECHNOLOGIES INC.Inventors: Shih-Kuang Chiu, Chia-Wei Yeh, Juei-Tsung Chen
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Publication number: 20230072193Abstract: A buckle device capable of displaying a locked state includes a main body unit, a latch unit, a fastening unit, an electromagnetic unit, and a control unit. The main body unit includes a main body and the latch unit includes a detachable tongue element. The fastening unit includes a bolt body interfering with the tongue element. The electromagnetic unit includes an electromagnetic module and an electromagnetic rod. The electromagnetic module controls the electromagnetic rod to interfere with the bolt body. The control unit includes a control module, a display module and a magnetic rod detection module for detecting the position of the electromagnetic rod. The control unit receives detection information of the magnetic bolt detection module and controls the display module to display a current state according to the position of the at least one electromagnetic rod.Type: ApplicationFiled: August 17, 2022Publication date: March 9, 2023Inventors: Shih-Kuang CHIU, Chia-Wei YEH, Juei-Tsung CHEN
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Patent number: 11213102Abstract: A buckle device comprises a main body unit, a latch unit and a fastening unit. The main body unit includes a housing surrounding and defining an accommodating space, two first apertures provided in the housing, two slider blocks arranged in the accommodating space, and two first elastic bodies abutting against the slider blocks. The latch unit includes a tongue element and two tongue openings provided on the tongue element. The fastening unit includes two bolt bodies passing through the first apertures, and two second elastic bodies abutting against the bolt bodies. When the tongue element is separated from the two slider blocks, the two slider blocks are pushed by the two first elastic bodies, and the two bolt bodies is pushed against by the two slider blocks.Type: GrantFiled: September 24, 2020Date of Patent: January 4, 2022Assignee: BROGENT TECHNOLOGIES INC.Inventor: Shih-Kuang Chiu
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Patent number: 10950507Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.Type: GrantFiled: May 7, 2018Date of Patent: March 16, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
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Patent number: 10772390Abstract: A buckle device comprises a main unit, a disk unit, a press unit, and an elastic unit. The main unit includes a housing. The disk unit includes at least one vertical disk. The press unit includes a press body. The elastic unit includes a first spring body. One end of the first spring body is disposed on the vertical disk. The other end of the first spring body is disposed on the press body. The first spring body is a thrust spring to extend the lifespan of the buckle device.Type: GrantFiled: October 16, 2019Date of Patent: September 15, 2020Assignee: BROGENT TECHNOLOGIES INC.Inventors: Shih-Kuang Chiu, Po-Tsun Chen, Juei-Tsung Chen
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Publication number: 20200221830Abstract: A buckle device comprises a main unit, a disk unit, a press unit, and an elastic unit. The main unit includes a housing. The disk unit includes at least one vertical disk. The press unit includes a press body. The elastic unit includes a first spring body. One end of the first spring body is disposed on the vertical disk. The other end of the first spring body is disposed on the press body. The first spring body is a thrust spring to extend the lifespan of the buckle device.Type: ApplicationFiled: October 16, 2019Publication date: July 16, 2020Inventors: Shih-Kuang CHIU, Po-Tsun CHEN, Juei-Tsung CHEN
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Patent number: 10615055Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.Type: GrantFiled: December 19, 2018Date of Patent: April 7, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20190246988Abstract: A physiological signal correction device, a correction method, and a wearable device with a correction function are provided. The physiological signal correction device includes a physiological signal sensor, a warping sensor, and a signal processing device. The physiological signal sensor is attached to an object to be detected to obtain a physiological signal value from at least one sensing electrode. The warping sensor is disposed on the physiological signal sensor and detects whether a warping condition of the physiological signal sensor with respect to the object to be detected occurs. The signal processing device corrects the physiological signal value provided by the physiological signal sensor according to the warping condition. The warping condition is caused by a distance between a part of the sensing electrode and the object to be detected or a change in a contact area between a part of the sensing electrode and the object to be detected.Type: ApplicationFiled: January 31, 2019Publication date: August 15, 2019Applicant: Industrial Technology Research InstituteInventors: Ming-Huan Yang, Cheng-Chung Lee, Shih-Kuang Chiu, Kuang-Ching Fan
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Publication number: 20190122898Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.Type: ApplicationFiled: December 19, 2018Publication date: April 25, 2019Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20190103360Abstract: A flexible chip package is provided. The flexible chip package includes a first flexible substrate; a first redistribution layer disposed on the first flexible substrate; a second flexible substrate; a second redistribution layer disposed on the second flexible substrate; a semiconductor chip disposed between the first and second redistribution layers and electrically connected to at least one of the first and second redistribution layers; and a first bonding layer disposed between the first and second redistribution layers and encapsulating the semiconductor chip, wherein the first bonding layer, the first redistribution layer and the second redistribution layer are between the first flexible substrate and the second flexible substrate.Type: ApplicationFiled: March 13, 2018Publication date: April 4, 2019Applicants: Industrial Technology Research Institute, Intellectual Property Innovation CorporationInventors: Cheng-Hung Yu, Tai-Jui Wang, Chieh-Wei Feng, Shih-Kuang Chiu, Ming-Huan Yang
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Patent number: 10199239Abstract: A package structure is provided, which includes: a frame having a cavity penetrating therethrough; a semiconductor chip received in the cavity of the frame, wherein the semiconductor chip has opposite active and inactive surfaces exposed from the cavity of the frame; a dielectric layer formed in the cavity to contact and fix in position the semiconductor chip, wherein a surface of the dielectric layer is flush with a first surface of the frame toward which the active surface of the semiconductor chip faces; and a circuit structure formed on the surface of the dielectric layer flush with the first surface of the frame and electrically connected to the active surface of the semiconductor chip, thereby saving the fabrication cost and reducing the thickness of the package structure.Type: GrantFiled: August 11, 2015Date of Patent: February 5, 2019Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20180254227Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.Type: ApplicationFiled: May 7, 2018Publication date: September 6, 2018Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
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Patent number: 10049955Abstract: A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.Type: GrantFiled: April 26, 2017Date of Patent: August 14, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Patent number: 9991178Abstract: An interposer is provided which includes: a substrate having a first surface with a plurality of first conductive pads and a second surface opposite to the first surface, the second surface having a plurality of second conductive pads; a plurality of conductive through holes penetrating the first and second surfaces of the substrate and electrically connecting the first and second conductive pads; and a first removable electrical connection structure formed on the first surface and electrically connecting a portion of the first conductive pads so as to facilitate electrical testing of the interposer.Type: GrantFiled: September 14, 2012Date of Patent: June 5, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Lu-Yi Chen, Chi-Hsin Chiu, Shih-Kuang Chiu
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Publication number: 20180125172Abstract: A latch device comprises a housing unit, a disk unit, an electromagnetic lock unit, a pressing lock unit, and a detecting unit. The housing unit includes a housing, which has a pressing hole and an insertion slot. The disk unit includes a supporting rod positioned through the housing, and two vertical disks pivotally arranged to the supporting rod. The outer perimeter of the two disks is placed with a hook, a first engaging portion and a second engaging portion. The electromagnetic lock unit includes two electromagnetic mechanisms, two retractable bars connected to the two electromagnetic mechanisms, and two electromagnetic latches respectively connected to the two retractable bars. The pressing lock unit includes a pushbutton, and a button latch connected to the pushbutton. The detecting unit includes two detectors, which are disposed inside the housing for detecting the position of the two electromagnetic latches.Type: ApplicationFiled: October 19, 2017Publication date: May 10, 2018Inventors: Ke-Cheng Chien, Wei-Ching Tang, Chih-Chiang Huang, Guo-Sen Lian, Shih-Kuang Chiu
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Patent number: 9899237Abstract: A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.Type: GrantFiled: February 7, 2014Date of Patent: February 20, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu
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Patent number: 9899308Abstract: A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.Type: GrantFiled: February 16, 2017Date of Patent: February 20, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Wen-Tsung Tseng, Yi-Che Lai, Shih-Kuang Chiu, Mao-Hua Yeh
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Patent number: 9875981Abstract: A semiconductor device is provided, including: a substrate having opposing first and second surfaces and a plurality of conductive vias passing through the first and second surfaces; an insulating layer formed on the first surface of the substrate and exposing end portions of the conductive vias therefrom; and a buffer layer formed on the insulating layer at peripheries of the end portions of the conductive vias, thereby increasing product reliability and good yield.Type: GrantFiled: October 19, 2016Date of Patent: January 23, 2018Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Meng-Tsung Lee, Yi-Che Lai, Shih-Kuang Chiu
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Patent number: 9812340Abstract: A method of fabricating a semiconductor package is provided, including: disposing a plurality of semiconductor elements on a carrier through an adhesive layer in a manner that a portion of the carrier is exposed from the adhesive layer; forming an encapsulant to encapsulate the semiconductor elements; removing the adhesive layer and the carrier to expose the semiconductor elements; and forming a build-up structure on the semiconductor elements. Since the adhesive layer is divided into a plurality of separated portions that will not affect each other due to expansion or contraction when temperature changes, the present invention prevents positional deviations of the semiconductor elements during a molding process, thereby increasing the alignment accuracy.Type: GrantFiled: March 18, 2016Date of Patent: November 7, 2017Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chiang-Cheng Chang, Meng-Tsung Lee, Jung-Pang Huang, Shih-Kuang Chiu, Fu-Tang Huang
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Patent number: D1020435Type: GrantFiled: November 8, 2021Date of Patent: April 2, 2024Assignee: BROGENT TECHNOLOGIES INC.Inventors: Shih-Kuang Chiu, Chia-Wei Yeh, Juei-Tsung Chen