Abstract: A flip-chip semiconductor device is proposed, including a substrate, a plurality of stiffeners disposed at peripheral areas of the substrate, with a gap formed between each of the adjacent stiffeners; at least a semiconductor chip mounted on an area of the substrate surrounded by the stiffeners via flip-chip technique; and a beat sink attached to the semiconductor chip. By such arrangement, warpage of the semiconductor device may be prevented. As an opening is formed at an appropriate position of the stiffener structure, distortion of the stiffener may be avoided. Further, as the beat sink is not attached to the stiffener, solder bumps may be free from thermal stress due to mismatch in coefficient of thermal expansion between the heat sink and the substrate while preventing delamination of the heat sink caused by thermal stress.

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; at least one chip mounted on the top surface of the substrate and electrically connected to the substrate; a heat sink attached to the top surface of the substrate by an adhesive material applied therebetween; and a plurality of solder balls implanted on the bottom surface of the substrate. The heat sink has a flat portion and a support portion connected to the flat portion. The support portion has at least one recess portion facing toward the top surface of the substrate and at least one burr formed on an interior surface of the recess portion such that the adhesive material can fill the recess portion and submerge the burr to provide an anchoring effect to firmly secure the heat sink in position on the substrate.

Abstract: A semiconductor package includes a substrate having a top surface and a bottom surface; at least one chip mounted on the top surface of the substrate and electrically connected to the substrate; a heat sink attached to the top surface of the substrate by an adhesive material applied therebetween; and a plurality of solder balls implanted on the bottom surface of the substrate. The heat sink has a flat portion and a support portion connected to the flat portion. The support portion has at least one recess portion facing toward the top surface of the substrate and at least one burr formed on an interior surface of the recess portion such that the adhesive material can fill the recess portion and submerge the burr to provide an anchoring effect to firmly secure the heat sink in position on the substrate.

Abstract: A substrate structure of Flip Chip package includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of first mounting pads and a plurality of second mounting pads. The solder mask layer covers the patterned circuit layer on the surface of the substrate, and a portion of the surface of the outer edge of the mounting pads while exposes a portion of the surface of the first mounting pads and the whole surface of the second mounting pads.

Abstract: A flip-chip bumping method is proposed for the fabrication of solder bumps on a semiconductor wafer for flip-chip application. The proposed flip-chip bumping method is intended for use on a semiconductor wafer predefined with a plurality of chip regions which are delimited from each other by a predefined cutting line and each of which is formed with a plurality of aluminum or copper based bond pads, and is characterized in the provision of a plating bus over and along the cutting line and connected to each bond pad. By means of this plating bus, the required UBM (Under Bump Metallization) fabrication and solder-bump fabrication can be both carried out through plating. Since plating process is considerably lower in cost than sputtering process and etching process, the proposed flip-chip bumping method can be more cost-effective to implement than prior art.

Abstract: An advanced flip-chip packaging technology is proposed, which is characterized in the forming of a metal dam over the substrate to serve three different utilization purposes. First, the metal dam can help provide a specific fillet width to the underfilled material under the flip chip so as to allow the joint between the flip chip and the substrate to have increased robustness against thermal stress. Second, the metal dam can serve as a mechanical reinforcement to the substrate to prevent package warpage. Third, the metal dam can additionally serve as a heat-dissipation structure to help the heat dissipation from the flip chip. These benefits allow the finished package product to be highly assured in quality and reliability.

Abstract: A semiconductor package structure with a heat-dissipation stiffener and a method of fabricating the same are proposed. The proposed packaging technology includes a substrate; a thermally-conductive stiffener mounted over the front surface of the substrate, the stiffener being formed with a centrally-hollowed portion and an outward-extending passage; a semi-conductor chip mounted on the front surface of the substrate and within the centrally-hollowed portion of the stiffener; an underfill layer filled and cured in a gap between the semiconductor chip and the substrate; and a plurality of solder balls mounted on the back surface of the substrate. Alternatively, the passage can be formed in the front surface of the substrate. During fabrication process, the passage is used for the injection of a cleaning solvent into the gap between the semiconductor chip and the substrate so as to clean away remnant solder flux.

Abstract: A semiconductor package structure with a heat-dissipation stiffener and a method of fabricating the same are proposed. The proposed packaging technology includes a substrate; a thermally-conductive stiffener mounted over the front surface of the substrate, the stiffener being formed with a centrally-hollowed portion and an outward-extending passage a semiconductor chip mounted on the front surface of the substrate and within the centrally-hollowed portion of the stiffener; an underfill layer filled and cured in a gap between the semiconductor chip and the substrate; and a plurality of solder balls mounted on the back surface of the substrate. Alternatively, the passage can be formed in the front surface of the substrate. During fabrication process, the passage is used for the injection of a cleaning solvent into the gap between the semiconductor chip and the substrate so as to clean away remnant solder flux.

Abstract: A flip-chip underfill method is proposed for the purpose of underfilling a gap formed beneath a semiconductor chip mounted in a flip-chip manner over an underlying surface. The flip-chip underfill method comprises the following procedural steps of: preparing a dispensing needle having an outlet; then, moving the dispensing needle in such a manner as to position the outlet thereof at a corner point between the upper surface and the sidewall of the semiconductor chip; and finally injecting resin at the targeted corner point, which allows the injected resin from the outlet of the dispensing needle to flow down along the sidewall of the semiconductor chip to the edge of the lower surface of the semiconductor chip and subsequently fill into the gap through capillary action.

Abstract: A flip-chip packaging process is proposed, which can help assure reliable electrical bonding between chip-side solder bumps and substrate-side bond pads without being made open-circuited by the electrically-insulative material being used for flip chip underfill. The proposed flip-chip packaging process is of the type utilizing a no-flow underfill technique to prevent short-circuiting between neighboring solder bumps, and is characterized in the fabrication of electrically-conductive sharp-pointed studs over substrate-side bond pads to prevent open-circuiting between chip-side solder bumps and substrate-side bond pads.

Abstract: A flip chip semiconductor package is proposed, in which a dam structure is formed of an adhesive compound such as epoxy resin on a substrate around a chip. The adhesive compound has a larger coefficient of thermal expansion than that of the substrate, and generates a greater thermal contraction force for counteracting thermal stress of the substrate in a cooling process in fabrication, so as to maintain planarity and structural intactness of the substrate and chip. Moreover, the chip can be made in a manner as to expose a non-active surface thereof to the atmosphere for facilitating dissipation of heat generated by the chip, while a heat sink can be additionally disposed on the chip, so as to further improve heat dissipating efficiency of the semiconductor package.

Abstract: An advanced flip-chip packaging technology is proposed, which is characterized in the forming of a metal dam over the substrate to serve three different utilization purposes. First, the metal dam can help provide a specific fillet width to the underfilled material under the flip chip so as to allow the joint between the flip chip and the substrate to have increased robustness against thermal stress. Second, the metal dam can serve as a mechanical reinforcement to the substrate to prevent package warpage. Third, the metal dam can additionally serve as a heat-dissipation structure to help the heat dissipation from the flip chip. These benefits allow the finished package product to be highly assured in quality and reliability.

Abstract: A flip chip semiconductor package is proposed, in which a dam structure is formed of an adhesive compound such as epoxy resin on a substrate around a chip. The adhesive compound has a larger coefficient of thermal expansion than that of the substrate, and generates a greater thermal contraction force for counteracting thermal stress of the substrate in a cooling process in fabrication, so as to maintain planarity and structural intactness of the substrate and chip. Moreover, the chip can be made in a manner as to expose a non-active surface thereof to the atmosphere for facilitating dissipation of heat generated by the chip, while a heat sink can be additionally disposed on the chip, so as to further improve heat dissipating efficiency of the semiconductor package.

Abstract: A flip-chip bonding structure on substrate for flip-chip package application is proposed, on which solder bumps can be bonded for electrically coupling a flip chip to the substrate. The proposed flip-chip bonding structure is characterized in that its solder-bump pads can be dimensionally-invariable irrespective of a positional deviation in solder mask due to misalignment. Moreover, the proposed flip-chip bonding structure can help allow each attached solder bump to be reduced in horizontal extent as compared to the prior art, so that neighboring solder bumps would be less likely short-circuited to each other and flip-chip underfill can be more easily implemented.

Abstract: A flip-chip bonding structure with stress-buffering property is proposed, which can help prevent cracking and warpage to the flip-chip construction due to thermal stress. The proposed flip-chip bonding structure used to bond a flip chip to a substrate, and is characterized in the provision of a first electrically-conductive stress-buffering layer over the chip-side bond pad and a second electrically-conductive stress-buffering layer over the substrate-side bond pad, so that under high-temperature conditions, the thermal stress from the flip chip can be buffered by the first electrically-conductive stress-buffering layer, while the thermal stress from the substrate can be buffered by the second electrically-conductive stress-buffering layer, thus preventing cracking and warpage to the flip-chip construction. As a result, the finished flip-chip package can be more assured in quality and reliability than the prior art.

Abstract: An underfill method is proposed for performing flip-chip underfill in an integrated circuit package of the type based on a WBCOCBGA (Wire-Bonded Chip-On-Chip Ball-Grid Array) construction which includes two semiconductor chips arranged in a chip-on-chip (COC) manner, wherein the underlying chip is electrically coupled to the substrate by means of wire bonding (WB), while the overlying chip is mounted in a flip-chip manner over the underlying chip and electrically coupled to the same by means of ball grid array (BGA) technology. The proposed method is characterized in the forming of an elongated dam structure over a preserved side surface area of the underlying chip beside the bonding wires connected to the underlying chip. During the dispensing process, the dispensed resin can fill into the gap under the overlying chip through capillary action while being prevented from coming in touch with the nearby bonding wires by the dam structure.

Abstract: An advanced flip-chip packaging technology is proposed, which is characterized in the forming of a metal dam over the substrate to serve three different utilization purposes. First, the metal dam can help provide a specific fillet width to the underfilled material under the flip chip so as to allow the joint between the flip chip and the substrate to have increased robustness against thermal stress. Second, the metal dam can serve as a mechanical reinforcement to the substrate to prevent package warpage. Third, the metal dam can additionally serve as a heat-dissipation structure to help the beat dissipation from the flip chip. These benefits allow the finished package product to be highly assured in quality and reliability.

Abstract: A bump structure formed having dopants therein. The bump structure includes a substrate, a plurality of bonding pads, a die and a plurality of bumps. The substrate has a first surface. The plurality of bonding pads is formed on the first surface of the substrate. The die has an active surface. Each bump at least includes a base and a plurality of dopants. The bumps are formed on the active surface of the die. The active surface of the die faces the first surface of the substrate. The substrate and the die are aligned such that each bump on the die corresponds with a bonding pad on the substrate. Dopants in the bump structure are made to contact the bonding pads on the substrate.