Abstract: An antenna structure and an electronic device are provided. The antenna structure is disposed on a carrier of the electronic device and includes a first dipole radiating element perpendicular to a plane, a second dipole radiating element connected to the first dipole radiating element, and a third dipole radiating element connected to the first dipole radiating element and the second dipole radiating element. The first dipole radiating element is configured to generate a first radiation pattern, the second dipole radiating element is configured to generate a second radiation pattern, and the third radiating element is configured to generate a third radiation pattern. The first radiation pattern is omnidirectional radiation on the plane. A polarization direction of the second radiation pattern and a polarization direction of the third radiation pattern are respectively orthogonal to a polarization direction of the first radiation pattern.

Abstract: An instant intelligent communication system for strangers is disclosed. The system includes a registration module, a business management module and a communication module. The registration module generates a personal unique identification code. The business management module issues or acquires business information. The communication module initiates a communication establishment request according to the personal unique identification code or the business information. The communication establishment module receives the communication establishment request and establish communication. The communications can be initiated and established through the business information issued on the Internet platform server, so that the business docketing is formed, and the business communication capability is greatly facilitated.

Abstract: Systems and methods for conducting critical dimension metrology are disclosed. According to certain embodiments, a charged particle beam apparatus generates a beam for imaging a first area and a second area. Measurements are acquired corresponding to a first feature in the first area, and measurements are acquired corresponding to a second feature in the second area. The first area and the second area are at separate locations on a sample. A combined measurement is calculated based on the measurements of the first feature and the measurements of the second feature.

Abstract: Disclosed herein is a method comprising: generating a plurality of probe spots on a sample by a plurality of beams of charged particles; while scanning the plurality of probe spots across a region on the sample, recording from the plurality of probe spots a plurality of sets of signals respectively representing interactions of the plurality of beams of charged particles and the sample; generating a plurality of images of the region respectively from the plurality of sets of signals; and generating a composite image of the region from the plurality of images.

Abstract: Systems and methods for conducting critical dimension metrology are disclosed. According to certain embodiments, a charged particle beam apparatus generates a beam for imaging a first area and a second area. Measurements are acquired corresponding to a first feature in the first area, and measurements are acquired corresponding to a second feature in the second area. The first area and the second area are at separate locations on a sample. A combined measurement is calculated based on the measurements of the first feature and the measurements of the second feature.

Abstract: Systems and methods for conducting critical dimension metrology are disclosed. According to certain embodiments, a charged particle beam apparatus generates a beam for imaging a first area and a second area. Measurements are acquired corresponding to a first feature in the first area, and measurements are acquired corresponding to a second feature in the second area. The first area and the second area are at separate locations on a sample. A combined measurement is calculated based on the measurements of the first feature and the measurements of the second feature.

Abstract: Systems and methods for conducting critical dimension metrology are disclosed. According to certain embodiments, a charged particle beam apparatus generates a beam for imaging a first area and a second area. Measurements are acquired corresponding to a first feature in the first area, and measurements are acquired corresponding to a second feature in the second area. The first area and the second area are at separate locations on a sample. A combined measurement is calculated based on the measurements of the first feature and the measurements of the second feature.

Abstract: Disclosed herein is a method comprising: generating a plurality of probe spots on a sample by a plurality of beams of charged particles; while scanning the plurality of probe spots across a region on the sample, recording from the plurality of probe spots a plurality of sets of signals respectively representing interactions of the plurality of beams of charged particles and the sample; generating a plurality of images of the region respectively from the plurality of sets of signals; and generating a composite image of the region from the plurality of images.

Abstract: Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

Abstract: A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

Abstract: Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

Abstract: Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: The installation position pointer system comprises a laser source to supply a laser beam, a driving device to align the laser beam, a controller device to control the operation of the driving device in accordance with an installation position data (IPD) of an attachment to be installed in a building and an associated reference position in the building, and an input device to obtain the IPD of a plurality of attachments from the attachment. The IPD of the attachments may be provided by an attachment installation position database system.

Abstract: Providing for a configuration cells for junction nodes of a field programmable gate array (FPGA) is described herein. By way of example, a configuration cell can comprise non-volatile resistive switching memory to facilitate programmable storage of data as an input to a control circuit of a junction node. The control circuit can activate or deactivate a junction node of the FPGA in response to a value of the data stored in the non-volatile resistive switching memory. The control circuit can comprise an SRAM circuit for fast operation of the junction node. Moreover, the non-volatile memory of the configuration cell facilitates fast power-up of the control circuit utilizing data stored in the resistive switching memory, and minimizes power consumption associated with storing the data.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data.

Abstract: Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.

Abstract: Integrated circuits with memory elements are provided. An integrated circuit may include logic circuitry formed in a first portion having complementary metal-oxide-semiconductor (CMOS) devices and may include at least a portion of the memory elements and associated memory circuitry formed in a second portion having nano-electromechanical (NEM) relay devices. The NEM and CMOS devices may be interconnected through vias in a dielectric stack. Devices in the first and second portions may receive respective power supply voltages. In one suitable arrangement, the memory elements may include two relay switches that provide nonvolatile storage characteristics and soft error upset (SEU) immunity. In another suitable arrangement, the memory elements may include first and second cross-coupled inverting circuits. The first inverting circuit may include relay switches, whereas the second inverting circuit includes only CMOS transistors.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.