Abstract: A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an inverter of a configuration random access memory (CRAM) cell associated with an unused logic portion of the PLD. The programmable power signal deactivates at least a portion of a configuration cell associated with the unused logic portion. That is, the programmable power signal eliminates the source to drain leakage as the power provided to the configuration cell is at ground. In one embodiment, the programmable power signal is provided to both inverters of a cross coupled pair of inverters rather than a single one of the cross-coupled pair of inverters. A programmable logic device capable of minimizing standby power consumption is also included.

Abstract: Methods and systems are disclosed that provide multiple lithography exposures on a wafer, for example, using interference lithography and optical photolithography. Various embodiments may balance the dosage and exposure rates between the multiple lithography exposures to provide the needed exposure on the wafer. Other embodiments provide for assist features and/or may apply resolution enhancement to various exposures. In a specific embodiment, a wafer is first exposed using optical photolithography and then exposed using interference lithography.

Abstract: Methods and systems are disclosed that provide multiple lithography exposures on a wafer, for example, using interference lithography and optical photolithography. Various embodiments may balance the dosage and exposure rates between the multiple lithography exposures to provide the needed exposure on the wafer. Other embodiments provide for assist features and/or may apply resolution enhancement to various exposures. In a specific embodiment, a wafer is first exposed using optical photolithography and then exposed using interference lithography.

Abstract: Interference lithography (IL) system and methods are disclosed according to embodiments of the invention. Two beams of coherent light with a first phase difference expose a first interference pattern on a nonlinear photoresist. A second interference pattern may be exposed on the nonlinear photoresist using the same coherent light beams with a second phase difference. The difference between the first and second phase differences is between 70° and 270°. The ensuing pattern is a composite of the first and second interference patterns. The IL may employ a third and fourth light beam.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: A low-power low-voltage buffer with a half-latch is provided. The half-latch buffer design may provide increased speed without dramatically increasing power consumption.

Abstract: An in-plane switching (IPS) liquid crystal display device (100) includes pixel units each having a storage capacitor. The storage capacitor is formed by a common electrode (112), a drain electrode (103), and a counter electrode (110). The common electrode is electrically coupled with the counter electrode. The counter electrode substantially covers the drain electrode, for shielding unexpected coupling effects on the drain electrode due to data signals on a data line (101) driving other pixels of the liquid crystal display device.

Abstract: Integrated circuits such as programmable logic device integrated circuits have arrays of memory elements into which configuration data is loaded. The memory elements are formed form a pair of independently-powered cross-coupled inverters. Control circuitry generates a first inverter power supply signal and a second inverter power supply signal. The first and second inverter power supply signals are distributed to the inverters in the memory elements using pairs of inverter power distribution paths. When it is desired to reset the memory elements, the control circuitry takes the second power supply signal high before the first power supply signal. When it is desired to preset the memory elements, the control circuitry takes the second power supply high after the first power supply signal.

Abstract: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

Abstract: Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function. During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage. During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage. Data loading and reading circuitry loads data into the memory elements and reads data from the memory elements. Address signals are generated by the data loading and reading circuitry. The address signals may have larger voltage levels during data writing operations than during read operations.

Abstract: Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the programmable logic device to customize the programmable logic. To ensure that the transistors in the programmable logic are turned on properly, the memory elements are powered with an elevated power supply level during normal device operation. During data loading operations, the power supply level for the memory elements is reduced. Reducing the memory element power supply level during loading increases the write margin for the memory elements.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: The present invention relates to a system and methodology to facilitate I/O access to a computer storage medium in a predictable and efficient manner. A scheduling system is provided that mitigates the problem of providing differing levels of performance guarantees for disk I/O in view of varying levels of data access requirements. In one aspect, the scheduling system includes an algorithm or component that provides high performance I/O updates while maintaining high throughput to the disk in a bounded or determined manner. This is achieved by dynamically balancing considerations of I/O access time and latency with considerations of data scheduling requirements. Also, the system provides latency boundaries for multimedia applications as well as managing accesses for other applications.

Abstract: A voltage supplying apparatus using fuel cell to be a voltage source is provided. The voltage supplying apparatus comprises a fuel cell, a DC-DC voltage converter and a control circuit. The DC-DC voltage converter is used to receive the voltage outputted from the fuel cell and then output another voltage. Then, the voltages outputted from the fuel cell and the DC-DC voltage converter are combined to be the output voltage of the voltage supplying apparatus. The control circuit is used to control the operation of the DC-DC voltage converter according to magnitude of the output voltage of the voltage supplying apparatus.

Abstract: An improved automatic holding device utilizes a remote operating lever to carry out forward and reverse turning and control the hooks of two-hook gripper for ease and efficiency of the operation, comprising an inner base, a threaded sleeve and a two-hook gripper; wherein said inner base having a near inverted-U shape cross section, a center bolt at its topside, and a tapped bore at corners of the inner base at both sides of the center bolt; the threaded sleeve is associated with the center bolt of the inner base, the outer surface of upper portion of the threaded sleeve has external thread, and the lower portion of the threaded sleeve is a gradually downward enlarged cone portion; and the middle part of two-hook gripper has a transversal axle hole for insertion of pin-jointed element into the tapped bore of the inner base, while provides a recess bevel at both inner side of upper part of the two-hook gripper for contact with the cone portion of the threaded sleeve, and each inner side of lower part of the two

Abstract: An ultrasonic wave passes different fuels of different concentrations with different velocities. The present invention provides a detecting and controlling device where, by a non-touching method, a velocity for an ultrasonic wave in a first fuel with a first fuel concentration is measured. The velocity obtained is taken for a comparison with another velocity for the same ultrasonic wave in a fuel with a default fuel concentration so that the first fuel concentration of the fuel can be under controlled.

Abstract: A mobile apparatus with automatic detection and communication of voice and digital data. The mobile apparatus has a voice module for processing a voice signal and communication means for serial transmission and reception of a digital data signal. Also, the mobile apparatus includes a connector, a processor and a selection unit. The connector has a first, second and third terminal used to receive and transmit a first, second and third signal respectively. The processor detects the third signal periodically and employs conversion means for converting the first signal into a voltage value to set a selection signal when the third signal is detected at a predetermined state. According to the selection signal, the selection unit establishes a first path between the connector and the communication means or establishes a second path between the connector and the voice module to pass the first and the second signals.

Abstract: The present invention relates to a nondestructive method or inspecting defects of the cladding of a nuclear fuel rod, which is featured by a wave emitter obliquely discharging an inspection wave to an inspected tube and a receiver arranged at a side of the inspected tube with respect to the wave emitter. If liquid is accumulated inside the tube, the incident inspection wave will be refracted so that the receiver can receive the refracted inspection wave at a specific location. The method can determine whether liquid is accumulated inside the tube and further is able to detect the level of the liquid.