Abstract: The present invention relates to a nondestructive method or inspecting defects of the cladding of a nuclear fuel rod, which is featured by a wave emitter obliquely discharging an inspection wave to an inspected tube and a receiver arranged at a side of the inspected tube with respect to the wave emitter. If liquid is accumulated inside the tube, the incident inspection wave will be refracted so that the receiver can receive the refracted inspection wave at a specific location. The method can determine whether liquid is accumulated inside the tube and further is able to detect the level of the liquid.

Abstract: Methods for fabricating ion sensitive field effect transistors (ISFETs) with SnO2 extended gates. A SnO2 detection film is formed on a substrate by sol-gel technology to serve as an extended gate. The SnO2 detection film is electrically connected to a conductive wire, and an insulating layer is formed on the surface of the ISFET but part of the SnO2 detection film and the conductive wire are left exposed. The exposed conductive wire is electrically connected to a gate terminal of a MOS transistor.

Abstract: A low-capacitance laminate varistor has at least one pair of first and second inner electrodes; a varistor layer, formed by at least one pair of first and second outer electrodes and the varistor layer being laminated; and the first outer electrode and the second outer electrode are electrically connected to the first inner electrode and a second inner electrode, respectively. In the low-capacitance laminate varistor of the present invention, the first inner electrode and the second inner electrode are staggered and also formed on the same plane and parallel to one another so that the electrode surface of the first inner electrode does not face the electrode surface of the second inner electrode.

Abstract: A mobile apparatus with automatic detection and communication of voice and digital data. The mobile apparatus has a voice module for processing a voice signal and communication means for serial transmission and reception of a digital data signal. Also, the mobile apparatus includes a connector, a processor and a selection unit. The connector has a first, second and third terminal used to receive and transmit a first, second and third signal respectively. The processor detects the third signal periodically and employs conversion means for converting the first signal into a voltage value to set a selection signal when the third signal is detected at a predetermined state. According to the selection signal, the selection unit establishes a first path between the connector and the communication means or establishes a second path between the connector and the voice module to pass the first and the second signals.

Abstract: An appparatus for confining plasma within a process zone of a substrate processing chamber. In one aspect, an apparatus comprises an annular member having an upper mounting surface, an inner confinement wall, and an outer confinement wall. The apparatus is disposed on or otherwise connected to a gas distribution assembly of the processing chamber to prevent plasma edge effects on the surface of a substrate. The apparatus provides a plasma choke aperture that reduces the volume of the process zone around the periphery of the substrate thereby eliminating uneven deposition of material around the edge of the substrate.

Abstract: Techniques and circuitry are used to reduce noise at the output (136) of an integrated circuit. The control circuit of the output buffer may reduce ground or power noise, or both. The control circuitry includes a ramp control circuit (153, 163) and di/dt or noise detect circuit (155, 165). A slew rate of the ramp control circuit output (173, 175) is controlled by the di/dt detect circuit. The di/dt detect circuit adjusts the slew rate of the ramp control circuit depending on the noise at the supply node which may be power (182) or ground (185), or both. The di/dt detect circuit may also be used to increase the slew rate of the ramp control circuit output to provide better performance.

Abstract: An apparatus for confining plasma within a process zone of a substrate processing chamber. In one aspect, an apparatus comprises an annular member having an upper mounting surface, an inner confinement wall, and an outer confinement wall. The apparatus is disposed on or otherwise connected to a gas distribution assembly of the processing chamber to prevent plasma edge effects on the surface of a substrate. The apparatus provides a plasma choke aperture that reduces the volume of the process zone around the periphery of the substrate thereby eliminating uneven deposition of material around the edge of the substrate.

Abstract: A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).

Abstract: A gas feedthrough in a semiconductor processing apparatus comprises a static-dissipative composite material. This material is characterized by good resistance to electromigration and is preferably made of a homogeneous material. This apparatus for preventing the transfer of energy to a gas flown through a gas line and comprises a gas feedthrough comprising a static-dissipative material, the feedthrough having a first end for abuttingly contacting an electrically energized member and a second end for contacting a grounded member, the feedthrough defining a void therein along its length to house a gas line.

Abstract: A sense amplifier circuit for a memory integrated circuit provides good performance and relatively low power consumption. The circuitry includes a cascode output and a feedback (214) from the cascode output to a transistor (M1) to provide additional pull-up current at a bit line (206).

Abstract: Techniques and circuitry are used to reduce noise at the output (136) of an integrated circuit. The control circuit of the output buffer may reduce ground or power noise, or both. The control circuitry includes a ramp control circuit (153, 163) and di/dt or noise detect circuit (155, 165). A slew rate of the ramp control circuit output (173, 175) is controlled by the di/dt detect circuit. The di/dt detect circuit adjusts the slew rate of the ramp control circuit depending on the noise at the supply node which may be power (182) or ground (185), or both. The di/dt detect circuit may also be used to increase the slew rate of the ramp control circuit output to provide better performance.

Abstract: A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).

Abstract: A pass gate isolation circuit (140) provides voltages to isolation pass gates (120) to allow higher speed access of rows in the memory array (105). When a read access of the array occurs, the pass gate isolation circuit generates a dynamic high voltage level at its output (315). The output becomes a steady state high voltage determined by a high voltage keeper circuit (320) and a voltage clamp circuit (325). When a write access of the array occurs, the pass gate isolation circuit generates an output level sufficient to permit addressing of the array and isolation of the row decoders (140).

Abstract: A slew rate control circuit to control output slew rate according to a programmable reference signal. A slew rate control circuit limits the slew rate of a plurality output buffers according to a signal received from a programmable slew rate control reference.

Abstract: A GRA cell used in logic for digital systems has a master/slave latch circuit which has a L1 master latch circuit and an L2 slave latch circuit. The L1 master latch circuit having a first cross-coupled portion and a complementary write circuit coupled to the slave latch and having scan-in port coupled to pass a scan-in signal to an L1 pass gate NFET transistor. An A.sub.-- Clock terminal port is connected to the L1 pass gate NFET transistor. The L2 slave latch's input is an output from the L1 master latch circuit. This L2 slave latch includes a second cross-coupled portion and a complementary write circuit. The L2 slave latch circuit is coupled to receive a signal resulting from the scan-in signal via said L1 latch circuit and an L2 pass gate NFET transistor for testing of said master/slave latch circuit. A B.sub.-- Clock terminal is connected to the L2 pass gate NFET transistor. This allows testing to be used with the single NFET pass gate transistors for each latch.

Abstract: A GRA cell used in logic for digital systems has a master/slave latch circuit which has a L1 master latch circuit and an L2 slave latch circuit. The L1 master latch circuit having a first cross-coupled portion and a complementary write circuit coupled to the slave latch and having scan-in port coupled to pass a scan-in signal to an L1 pass gate NFET transistor. An A.sub.-- Clock terminal port is connected to the L1 pass gate NFET transistor. The L2 slave latch's input is an output from the L1 master latch circuit. This L2 slave latch includes a second cross-coupled portion and a complementary write circuit. The L2 slave latch circuit is coupled to receive a signal resulting from the scan-in signal via said L1 latch circuit and an L2 pass gate NFET transistor for testing of said master/slave latch circuit. A B.sub.-- Clock terminal is connected to the L2 pass gate NFET transistor. This allows testing to be used with the single NFET pass gate transistors for each latch.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.

Abstract: A split random access memory array is integrated with a read only storage array and shares the same sense and bit decode circuitry. Each bit line of the integrated array is provided with an isolation switch between the random access and read only portions. The switch conducts when reading the read only portion but does not conduct (isolates) when writing or reading the random access portion. The isolation switch also permits the initialization of the shared differential sensing latch and facilitates the rapid writing and reading of the random access portion by removing the bit line loading due to the read only portion on such occasions.

Abstract: A user configurable circuit contains clock logic, a switching element and a data path circuit. Input data is received in the switching element, and the switching element and the data path circuit constitute the entire data path for the circuit. A plurality of user configurable inputs are received to configure the circuit for a particular user application. The clock logic and the switching element implement a logic function that is configurable by the user configurable inputs. The logic function is pre-processed in the clock logic so that minimal delay occurs in the data path. In addition, the propagation delay through the switching element and the register is independent of the user configurable inputs. The user configurable circuit of the present invention has application for use as a macro cell for a programmable logic device permitting the user to configure the circuit as a D-type flip-flop, a T-type flip-flop. In addition, the user selects the polarity for the output circuit.