Abstract: Memory elements may be provided that include bi-stable data storage elements based on cross-coupled inverters. A pair of address transistors may be used to implement a differential data writing scheme for the memory elements. One of the address transistors may be coupled between a first data line and a first data storage node in each memory element and another of the address transistors may be coupled between a second data line and a second data storage node. A read circuit may be coupled to the second data storage node. Clear transistors may be interspersed through the array. The clear transistors may help pull the data lines to desired voltages during clear operations. An adjustable power supply may supply a weakened power supply voltage to a pull-up clear transistor and to the first and second inverters during clear operations.

Abstract: One embodiment relates to a buffered transistor device. The device includes a buffered vertical fin-shaped structure formed in a semiconductor substrate. The vertical fin-shaped structure includes at least an upper semiconductor layer, a buffer region, and at least part of a well region. The buffer region has a first doping polarity, and the well region has a second doping polarity which is opposite to the first doping polarity. At least one p-n junction that at least partially covers a horizontal cross section of the vertical fin-shaped structure is formed between the buffer and well regions. Other embodiments, aspects, and features are also disclosed.

Abstract: A solar panel and an electrode structure thereof and a manufacturing method thereof are provided. The electrode structure comprises a first conductive structure and a second conductive structure. The first conductive structure is electrically connected to a plurality of first pole contacts of a first solar cell. The second conductive structure is connected to the first conductive structure, and the first and the second conductive structures are substantially extended along a line. The second conductive structure is electrically connected to a plurality of second pole contacts of a second solar cell.

Abstract: Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.

Abstract: A solar cell panel is provided. The solar cell panel includes a solar cell module and a transparent substrate. The solar cell module includes a number of solar cells having a number of gaps. Each gap is located between any adjacent two of the solar cells. A transparent substrate is disposed above the solar cell module. The transparent substrate has a patterned structure which is right above the gaps.

Abstract: The patent disclose a multi-user local access and delivery control system which comprises at least one storage device including a plurality of controlled storage cavities and a plurality of mobile units, each comprising a plurality of lockable storage drawers and an ID information pickup device. Particular storage cavities and storage drawers are unlocked to allow a deliverer to remove items from the storage cavities and place them in the storage drawers. After being relocked, the storage drawers are unlocked only when designated receivers are identified.

Abstract: A turning mechanism for skateboards includes a plate fixed to the underside of the board and a wheel frame is pivotably connected to the pivot tube on the plate. A first part extends through a lug on the plate and a second part is threadedly connected to the first part. A U-shaped first restriction member extends through a spring and is connected to the second part, and two hook ends of the first restriction member are hooked to a first end of the spring. A U-shaped second restriction member extends through the spring and is connected to a rod on the wheel frame. Two hook ends of the second restriction member are hooked to a second end of the spring. The second part moves linearly to pull the spring when rotating the first part so as to restrict the required force that the wheel frame is pivoted relative to the pivot tube.

Abstract: An eddy current probe uses magnetic gap. The probe has a small size; and coil number in the probe is reduced. Hence, the probe can move easily inside and outside a tube and detect an end of the tube as close as possible.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The core logic is powered using a core logic power supply level defined by a core logic positive power supply voltage and a core logic ground voltage. When loaded with configuration data, the memory elements produce output signals that are applied to the gates of the transistors in the core logic to customize the programmable logic device. The memory elements are powered with a memory element power supply level defined by a memory element positive power supply voltage and a memory element ground power supply voltage. The memory element power supply level is elevated with respect to the core logic power supply level.

Abstract: A turning mechanism for skateboards includes a plate fixed to the underside of the board and a wheel frame is pivotably connected to the pivot tube on the plate. A first part extends through a lug on the plate and a second part is threadedly connected to the first part. A U-shaped first restriction member extends through a spring and is connected to the second part, and two hook ends of the first restriction member are hooked to a first end of the spring. A U-shaped second restriction member extends through the spring and is connected to a rod on the wheel frame. Two hook ends of the second restriction member are hooked to a second end of the spring. The second part moves linearly to pull the spring when rotating the first part so as to restrict the required force that the wheel frame is pivoted relative to the pivot tube.

Abstract: Integrated circuits are provided that have memory elements. The memory elements may be organized in an array. Data such as programmable logic device configuration data may be loaded into the array using read and write control circuitry. Each memory element may store data using a pair of cross-coupled inverters. Power supply circuitry may be used to power the cross-coupled inverters. A positive power supply signal and a ground power supply signal may be provided to the inverters by the power supply circuitry. Each memory element may have an associated clear transistor. A clear control signal may be asserted to turn on the clear transistor when clearing the memory elements. A given one of the inverters in each memory element may be momentarily weakened with respect to the clear transistor in that memory element by using the power supply circuitry to temporarily elevate the ground power supply signal.

Abstract: An eddy current probe uses magnetic gap The probe has a small size; and coil number in the probe is reduced. Hence, the probe can move easily inside and outside a tube and detect an end of the tube as close as possible.

Abstract: Memory elements for integrated circuit are provided that have efficient transistor layouts. The integrated circuits may be programmable logic device integrated circuits on which memory elements are formed into arrays. Each memory element may have a pair of cross-coupled inverters, an address transistor, and a clear transistor. The transistors in each memory element may be formed from n-type and p-type semiconductor regions that are crossed by only three gate conductor fingers. Programmable transistors on the integrated circuit may be controlled by static output signals from the memory elements. The programmable transistors may be used to form multiplexers. The multiplexers may be formed from n-type regions that are crossed by only three gate fingers each. The gate fingers of the multiplexers may be aligned with the gate fingers of the transistor structures of the memory elements.

Abstract: The present invention relates to a system and methodology to facilitate I/O access to a computer storage medium in a predictable and efficient manner. A scheduling system is provided that mitigates the problem of providing differing levels of performance guarantees for disk I/O in view of varying levels of data access requirements. In one aspect, the scheduling system includes an algorithm or component that provides high performance I/O updates while maintaining high throughput to the disk in a bounded or determined manner. This is achieved by dynamically balancing considerations of I/O access time and latency with considerations of data scheduling requirements. Also, the system provides latency boundaries for multimedia applications as well as managing accesses for other applications.

Abstract: A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an inverter of a configuration random access memory (CRAM) cell associated with an unused logic portion of the PLD. The programmable power signal deactivates at least a portion of a configuration cell associated with the unused logic portion. That is, the programmable power signal eliminates the source to drain leakage as the power provided to the configuration cell is at ground. In one embodiment, the programmable power signal is provided to both inverters of a cross coupled pair of inverters rather than a single one of the cross-coupled pair of inverters. A programmable logic device capable of minimizing standby power consumption is also included.

Abstract: A lithography scanner and track system is provided that includes an interference lithography system according to one embodiment. The scanner provides a first optical exposure of a wafer. The track system provides pre and post-processing functions on a wafer. The interference lithography system may be included within the scanner and may expose a wafer either before or after the first optical exposure. The interference lithography system may also be included within the track system as part of the pre or post processing. The first optical exposure may include optical photolithography.

Abstract: An ultrasonic wave passes different fuels of different concentrations with different velocities. The present invention provides a detecting and controlling device where, by a non-touching method, a velocity for an ultrasonic wave in a first fuel with a first fuel concentration is measured. The velocity obtained is taken for a comparison with another velocity for the same ultrasonic wave in a fuel with a default fuel concentration so that the first fuel concentration of the fuel can be under controlled.

Abstract: A method for providing regular line patterns using interference lithography and sidewall patterning techniques is provided according to one embodiment. The method comprising may include producing regularly spaced parallel lines on a template using interference lithography techniques and then depositing sidewalls on the longitudinal sides of the regularly spaced parallel lines using sidewall patterning techniques. Various deposition and etching steps may also be included. The embodiments of the invention may provide regular line patterns with a line density half the interference lithography line density. Various lithography techniques may also be used to crop rounded connecting resulting from the sidewall patterning and/or to alter portions of the line pattern.

Abstract: A voltage supplying apparatus using fuel cell to be a voltage source is provided. The voltage supplying apparatus comprises a fuel cell, a DC-DC voltage converter and a control circuit. The DC-DC voltage converter is used to receive the voltage outputted from the fuel cell and then output another voltage. Then, the voltages outputted from the fuel cell and the DC-DC voltage converter are combined to be the output voltage of the voltage supplying apparatus. The control circuit is used to control the operation of the DC-DC voltage converter according to magnitude of the output voltage of the voltage supplying apparatus.