Patents by Inventor Shih-Ming Chang

Shih-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200028469
    Abstract: A calibration apparatus is used for calibrating characteristics of a power amplifier (PA) in a transmitter. The calibration apparatus includes an adaptive bias generator circuit that is used to track an envelope of an input signal received by control terminals of transistors of the PA and generate an adaptive bias voltage to the control terminals of the input transistors in response to the envelope of the input signal.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 23, 2020
    Inventors: Yu-Hsien Chang, Yu-Ming Lai, Ching-Chia Cheng, Wei-Kai Hong, Yi-Chu Chen, Tsung-Ming Chen, Shih-Chieh Yen
  • Publication number: 20200027750
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Publication number: 20200017414
    Abstract: The invention relates to a water-based ceramic three-dimensional laminate material and a method for using the same material to manufacture the ceramic objects, comprising: a step Sa of preparing a plurality of projected slice graphics and a slurry, wherein the projected slice graphics are formed by slicing a three-dimensional image along a specific direction with a specific thickness, the slurry is prepared by mixing the material powder, the photo-curing resin, the solvent and the additive; a step Sb of uniformly laying the slurry on the substrate to form a sacrificial layer; and a step Sc of uniformly laying the slurry on the slurry to form a reaction layer on the sacrificial layer; a step Sd of irradiating the reaction layer with a light beam according to one of the plurality of projected slice graphics, and the slurry is cured after being irradiated; a step Se of repeating steps Sc and Sd until a ceramic body is formed; a step Sf of washing the ceramic body with water or an organic solvent; and a step Sg o
    Type: Application
    Filed: May 6, 2019
    Publication date: January 16, 2020
    Inventors: Chun-Jung YEN, Feng-Ming YEN, Ching-Hsing CHANG, Chun-Yen TUNG, Shih-Wei CHENG
  • Publication number: 20200019853
    Abstract: A product testing system and an auxiliary testing method are provided. The product testing system includes a computer and a test fixture. The computer has a machine learning model. The auxiliary testing method includes the following steps. Firstly, the test fixture tests the plural under-test products sequentially, and generates corresponding test data to the computer. Then, the computer generates plural trend line graphs corresponding to the test data. Then, the operator determines corresponding human judging results according to the trend line graphs. The test data, the trend line graphs and the human judging results are inputted into the machine learning model, and a learning process is performed. If the number of samples reaches a predetermined threshold value, the machine learning model generates auxiliary judging results according to the corresponding test data and the corresponding trend line graphs.
    Type: Application
    Filed: November 15, 2018
    Publication date: January 16, 2020
    Inventors: Shih-Chieh Hsu, Pei-Ming Chang, Pao-Chung Chao, Wei-Lung Huang
  • Patent number: 10535646
    Abstract: Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10528693
    Abstract: An integrated circuit device includes first and second features, each including an end portion arranged along a common axis, and separated by a space. The end portion of the first feature includes a first indention adjacent to the space. The end portion of the second feature includes a first indention adjacent to the space, mirroring the first indention of the first feature about the space. The end portions are substantially similar in shape.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Kuei-Liang Lu
  • Publication number: 20200004137
    Abstract: A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 2, 2020
    Inventors: Ru-Gun LIU, Chin-Hsiang LIN, Cheng-I HUANG, Chih-Ming LAI, Lai Chien WEN, Ken-Hsien HSIEH, Shih-Ming CHANG, Yuan-Te HOU
  • Publication number: 20200006514
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Application
    Filed: September 4, 2019
    Publication date: January 2, 2020
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Patent number: 10521541
    Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; a first fin stub on the substrate, wherein the first fin stub connects a bottom portion of the first active fin and a bottom portion of the second active fin; and an isolation feature over the first fin stub and between the first and second active fins. The first fin stub is lower than both the first and the second active fins in height. The isolation feature is higher than the first fin stub and lower than both the first and the second active fins in height. From a top view, the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ming Wang, Chih-Hsiung Peng, Chi-Kang Chang, Kuei-Shun Chen, Shih-Chi Fu
  • Patent number: 10522464
    Abstract: A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the substrate feature; forming an etch mask over the first material layer; and applying a dynamic-angle (DA) plasma etching process to the first material layer through the etch mask to form a first material feature. Plasma flux of the DA plasma etching process has an angle of incidence with respect to a normal of the first material layer and the angle of incidence changes in a dynamic mode during the DA plasma etching process.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Tsung Shih
  • Patent number: 10514613
    Abstract: A pattern modification method and a patterning process are provided. The method includes extracting a first pattern and a second pattern to be respectively transferred to a first target portion and a second target portion of a resist layer. The method also includes obtaining regional information of the first target portion and the second target portion. The method includes determining a first desired focus position for transferring the first pattern based on the regional information. In addition, the method includes determining a second desired focus position for transferring the second pattern based on the regional information. The method includes modifying one or both of the first pattern and the second pattern. As a result, focus positions of the first pattern and the second pattern are shifted to be substantially and respectively positioned at the first desired focus position and the second desired focus position during an exposure operation.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Ru-Gun Liu, Shuo-Yen Chou, Chien-Wen Lai, Zengqin Zhao
  • Patent number: 10515823
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 10505224
    Abstract: An electrolyte is provided. The electrolyte includes a polymer, a lithium salt, and an organic solvent. The polymer is a polymerization product of a reactive additive and an initiator, wherein the reactive additive includes at least an amide group and at least an epoxy group or ethyl group. A composition for electrolyte and a lithium battery employing the electrolyte are also provided.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 10, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ting-Ju Yeh, Chia-Ming Chang, Tsung-Hsiung Wang, Cheng-Zhang Lu, Chia-Erh Liu, Shih-Chieh Liao
  • Patent number: 10503085
    Abstract: A lithography apparatus is provided. The lithography apparatus includes an exposure system and a fluid handling system. The exposure system is configured to expose an exposure area on a substrate with an energy flow. The fluid handling system is configured to provide a heat transfer fluid flowing through a non-exposure area other than the exposure area on the substrate, to take heat away from the substrate.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shih-Ming Chang
  • Publication number: 20190371606
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10495982
    Abstract: Disclosed is a lithography system. The lithography system includes a radiation source to provide radiation energy for lithography exposure; a substrate stage configured to secure a substrate; an imaging lens module configured to direct the radiation energy onto the substrate; at least one sensor configured to detect a radiation signal directed from the substrate; and a pattern extraction module coupled with the at least one sensor and designed to extract a pattern of the substrate based on the radiation signal.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Wen-Chuan Wang
  • Patent number: 10497565
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure. The method includes forming third spacers over second sidewalls of the second spacers. The method includes removing the filling layer and the second spacers.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
  • Patent number: 10491006
    Abstract: A hand-held apparatus and a method for power charging management thereof are provided. The method for power charging management includes: providing a power charging voltage and a power charging current to perform a power charging process to the hand-held apparatus, and simultaneously detecting a surface temperature of the hand-held apparatus during the power charging process; activating a power charging management mechanism when the surface temperature is higher than a reference temperature, and simultaneously reducing a voltage value of the power charging voltage; and generating a comparing result by comparing the surface temperature with a plurality of threshold temperatures after the power charging management mechanism is activated, and adjusting a current value of the power charging current based on the comparing result. The reference temperature is lower than the plurality of threshold temperatures and values of the plurality of threshold temperatures are not the same.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: November 26, 2019
    Assignee: HTC Corporation
    Inventors: Chuan-Li Wu, Chia-Ming Chang, Shih-Ping Lin
  • Patent number: 10488766
    Abstract: A lithography system is provided. The lithography system includes a mask and an optical module. The optical module is configured to optically form an invisible pellicle over the mask to protect the mask from contaminant particles. As a solid pellicle used in the prior arts is omitted, the critical dimension (CD) error from the boarder effect due to reflection of some light by the solid pellicle and the exposure radiation energy consumption caused by the solid pellicle can be avoided.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 26, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chiu-Hsiang Chen, Shih-Ming Chang, Chih-Jie Lee, Han-Wei Wu, Yung-Sung Yen, Ru-Gun Liu
  • Patent number: 10490643
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: November 26, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu