Patents by Inventor Shih-Ming Chang

Shih-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11010526
    Abstract: A semiconductor device includes a first active fin on a substrate; a second active fin on the substrate and separate from the first active fin; and a first fin stub on the substrate, wherein the first fin stub connects a first end of the first active fin and a first end of the second active fin, wherein the fin stub is lower than both the first and the second active fins in height, wherein from a top view the first active fin is oriented lengthwise in a first direction, and the first fin stub is oriented lengthwise in a second direction that is different from the first direction.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Ming Wang, Chih-Hsiung Peng, Chi-Kang Chang, Kuei-Shun Chen, Shih-Chi Fu
  • Patent number: 11004855
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Guo-Huei Wu, Yu-Jung Chang
  • Publication number: 20210132504
    Abstract: In one example, an apparatus includes an extreme ultraviolet illumination source and an illuminator. The extreme ultraviolet illumination source is arranged to generate a beam of extreme ultraviolet illumination to pattern a resist layer on a substrate. The illuminator is arranged to direct the beam of extreme ultraviolet illumination onto a surface of a photomask. In one example, the illuminator includes a field facet mirror and a pupil facet mirror. The field facet mirror includes a first plurality of facets arranged to split the beam of extreme ultraviolet illumination into a plurality of light channels. The pupil facet mirror includes a second plurality of facets arranged to direct the plurality of light channels onto the surface of the photomask. The distribution of the second plurality of facets is denser at a periphery of the pupil facet mirror than at a center of the pupil facet mirror.
    Type: Application
    Filed: May 28, 2020
    Publication date: May 6, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ken-Hsien HSIEH, Shih-Ming CHANG, Wen LO, Wei-Shuo SU, Hua-Tai LIN
  • Publication number: 20210118125
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10971363
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Ming Lai, Shih-Ming Chang, Wei-Liang Lin, Chin-Yuan Tseng, Ru-Gun Liu
  • Patent number: 10962892
    Abstract: A method of performing a lithography process includes providing a test pattern. The test pattern includes a first set of lines arranged at a first pitch, a second set of lines arranged at the first pitch, and further includes at least one reference line between the first set of lines and the second set of lines. The test pattern is exposed with a radiation source providing an asymmetric, monopole illumination profile to form a test pattern structure on a substrate. The test pattern structure is then measured and a measured distance correlated to an offset of a lithography parameter. A lithography process is adjusted based on the offset of the lithography parameter.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Jie Lee, Shih-Chun Huang, Shih-Ming Chang, Ken-Hsien Hsieh, Yung-Sung Yen, Ru-Gun Liu
  • Publication number: 20210080822
    Abstract: A method for forming a photomask is provided. The method includes forming a light blocking layer over a transparent substrate. The light blocking layer has a first portion, a second portion, and a connection portion. The method includes forming a mask layer over the first portion and the second portion of the light blocking layer. The method includes removing the connection portion. The method includes removing the mask layer. The second portion of the light blocking layer is removed during removing the mask layer, while the first portion remains. The method includes after removing the mask layer and the second portion, removing the third portion of the transparent substrate to form a first recess in the transparent substrate. The method includes forming a light blocking structure in the first recess.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 18, 2021
    Inventors: Shih-Ming CHANG, Minfeng CHEN, Min-An YANG, Shao-Chi WEI
  • Publication number: 20210055646
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Chien-Cheng CHEN, Chia-Jen CHEN, Hsin-Chang LEE, Shih-Ming CHANG, Tran-Hui SHEN, Yen-Cheng HO, Chen-Shao HSU
  • Patent number: 10930505
    Abstract: The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsong-Hua Ou, Ken-Hsien Hsieh, Shih-Ming Chang, Wen-Chun Huang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20210035862
    Abstract: The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.
    Type: Application
    Filed: June 4, 2020
    Publication date: February 4, 2021
    Inventors: Ru-Gun Liu, Shih-Ming Chang, Hoi-Tou Ng
  • Publication number: 20210018849
    Abstract: A method for taking heat away from the photomask includes driving a working fluid to flow between a photomask and a fluid retaining structure and through a first slit of the fluid retaining structure, such that a boundary of the working fluid is confined between the photomask and the fluid retaining structure; and generating a light to irradiate the photomask through a light transmission region of the fluid retaining structure.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 21, 2021
    Inventors: Shih-Ming Chang, Chiu-Hsiang Chen, Ru-Gun Liu
  • Patent number: 10872969
    Abstract: Manufacturing a semiconductor device includes forming a pad oxide layer on a semiconductor substrate. A hard mask layer is formed over the pad oxide layer. An anti-reflective layer (ARL) is formed over the hard mask layer. A first photoresist layer is formed over the ARL. The first photoresist layer is patterned and the hard mask layer and ARL are removed. Remaining portions of the first photoresist layer and the ARL are removed, and a patterned hard mask layer is formed. The pad oxide layer and the semiconductor substrate are etched to obtain a plurality of fins. A bottom layer is formed over and between the fins. A middle layer is formed over the bottom layer and a second photoresist layer is formed on the middle layer. The second photoresist layer is patterned to form an opening and a spacer is formed in an opening formed in the second photoresist layer.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shih-Ming Chang
  • Publication number: 20200393752
    Abstract: A method of operating a semiconductor apparatus includes forming a first electron beam passing through a first shaping aperture; modifying an energy distribution of the first electron beam by a second shaping aperture, such that the first electron beam has a main region and an edge region having a greater energy than the main region; and exposing a workpiece to the main region and the edge region of the first electron beam to create a pattern.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Inventors: Wen LO, Shih-Ming CHANG, Chun-Hung LIU
  • Patent number: 10845699
    Abstract: A method for forming a photomask is provided. The method includes forming a light blocking layer over a transparent substrate. The method includes forming a mask layer over the light blocking layer. The mask layer covers a first portion of the light blocking layer, and the first portion is over a second portion of the transparent substrate. The method includes removing the light blocking layer, which is not covered by the mask layer. The method includes removing the mask layer. The first portion of the light blocking layer is removed during removing the mask layer. The method includes removing the second portion of the transparent substrate to form a first recess in the transparent substrate. The method includes forming a first light blocking structure in the first recess.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Minfeng Chen, Min-An Yang, Shao-Chi Wei
  • Publication number: 20200350250
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Pochun WANG, Ting-Wei CHIANG, Chih-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Ya-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG
  • Patent number: 10816892
    Abstract: In a method of manufacturing a photo mask for lithography, circuit pattern data are acquired. A pattern density, which is a total pattern area per predetermined area, is calculated from the circuit pattern data. Dummy pattern data for areas having pattern density less than a threshold density are generated. Mask drawing data is generated from the circuit pattern data and the dummy pattern data. By using an electron beam from an electron beam lithography apparatus, patterns are drawn according to the mask drawing data on a resist layer formed on a mask blank substrate. The drawn resist layer is developed using a developing solution. Dummy patterns included in the dummy pattern data are not printed as a photo mask pattern when the resist layer is exposed with the electron beam and is developed.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chien-Cheng Chen, Chia-Jen Chen, Hsin-Chang Lee, Shih-Ming Chang, Tran-Hui Shen, Yen-CHeng Ho, Chen-Shao Hsu
  • Publication number: 20200301289
    Abstract: A method includes receiving a layout that includes a shape to be formed on a photomask and determining a plurality of target lithographic contours for the shape, wherein the plurality of target lithographic contours includes a first target lithographic contour for a first set of process conditions and a second target lithographic contour for a second set of process conditions, performing a lithographic simulation of the layout to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions, determining a first edge placement error between the first simulated contour and the first target lithographic contour and a second edge placement error between the second simulated contour and the second target lithographic contour, and determining a modification to the layout based on the first edge placement error and the second edge placement error.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
  • Publication number: 20200286738
    Abstract: A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a patterning process; and forming a second plurality of trenches in the first layer by another patterning process, resulting in combined trench patterns in the first layer. A first trench of the second plurality connects two trenches of the first plurality. The method further includes forming dielectric spacer features on sidewalls of the combined trench patterns. A space between two opposing sidewalls of the first trench is completely filled by the dielectric spacer features and another space between two opposing sidewalls of one of the two trenches is partially filled by the dielectric spacer features.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Inventors: RU-GUN LIU, CHENG-HSIUNG TSAI, CHUNG-JU LEE, CHIH-MING LAI, CHIA-YING LEE, JYU-HORNG SHIEH, KEN-HSIEN HSIEH, MING-FENG SHIEH, SHAU-LIN SHUE, SHIH-MING CHANG, TIEN-I BAO, TSAI-SHENG GAU
  • Patent number: 10770303
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10756016
    Abstract: A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the substrate feature; forming an etch mask over the first material layer; and applying a dynamic-angle (DA) plasma etching process to the first material layer through the etch mask to form a first material feature. Plasma flux of the DA plasma etching process has an angle of incidence with respect to a normal of the first material layer and the angle of incidence changes in a dynamic mode during the DA plasma etching process.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Tsung Shih