Patents by Inventor Shih-Ming Chang

Shih-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10345887
    Abstract: Methods and apparatus are provided for adaptive optimization of low-power strategies. In one novel aspect, the device monitors one or more thermal-performance parameters and determines a plurality of operation scenarios for a plurality of corresponding low-power policies. Based on corresponding operation scenarios, the device selects corresponding low-power policy. The device applies different low-power strategy for temperature control based on low-power policies. Different low-power policy is applied to different low-power techniques, such as the DVFS, the CPU hot-plug, and the task migration. In another novel aspect, the device obtains one or more user-defined policy for each corresponding low-power technique. The selection of each low-power policy is further based on its corresponding user-defined policy. In one embodiment, the user-defined DVFS policy includes power policy, performance policy, and DVFS-balanced policy.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: July 9, 2019
    Assignee: MEDIATEK INC.
    Inventors: Kuo-SU Hsiao, Yen-Lin Lee, Shih-Yen Chiu, Jia-Ming Chen, Mark Shane Peng, Ya-Ting Chang
  • Publication number: 20190207255
    Abstract: An electrolyte is provided. The electrolyte includes a polymer, a lithium salt, and an organic solvent. The polymer is a polymerization product of a reactive additive and an initiator, wherein the reactive additive includes at least an amide group and at least an epoxy group or ethyl group. A composition for electrolyte and a lithium battery employing the electrolyte are also provided.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Ting-Ju YEH, Chia-Ming CHANG, Tsung-Hsiung WANG, Cheng-Zhang LU, Chia-Erh LIU, Shih-Chieh LIAO
  • Patent number: 10340350
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: July 2, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10338978
    Abstract: An electronic device test system and method detects a memory serial number of an electronic device. The electronic device test system includes a Macintosh system computer, configured to execute a serial number detection program to detect the memory serial number of the electronic device; and a Windows system computer, configured to execute a serial number comparison program to compare whether the memory serial number of the electronic device satisfies a coding rule. The Macintosh system computer transmits the memory serial number to the Windows system computer by means of an RS232 interface for printing.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: July 2, 2019
    Assignee: PRIMAX ELECTRONICS LTD.
    Inventors: Pei-Ming Chang, Shih-Chieh Hsu
  • Publication number: 20190198867
    Abstract: A cathode of a lithium ion battery is provided. The cathode of a lithium ion battery includes a collector material. A first electrode layer including a lithium manganese iron phosphate (LMFP) material is disposed on a surface of the collector material. A second electrode layer including an active material is disposed on the first electrode layer. The active material includes lithium nickel manganese cobalt oxide (NMC), lithium nickel cobalt aluminum oxide (NCA), lithium cobalt oxide (LCO), Li-rich cathode material, or a combination thereof.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 27, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Ming CHANG, Shih-Chieh LIAO, Dar-Jen LIU, Wen-Bing CHU, Jin-Ming CHEN
  • Publication number: 20190198864
    Abstract: A cathode of a lithium ion battery is provided. The cathode of a lithium ion battery includes a collector material. A first electrode layer including a lithium manganese iron phosphate (LMFP) material is disposed on a surface of the collector material. A second electrode layer including an active material is disposed on the first electrode layer. The active material includes lithium nickel manganese cobalt oxide (NMC), lithium nickel cobalt aluminum oxide (NCA), lithium cobalt oxide (LCO), Li-rich cathode material, or a combination thereof.
    Type: Application
    Filed: March 30, 2018
    Publication date: June 27, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Ming CHANG, Shih-Chieh LIAO, Dar-Jen LIU, Wen-Bing CHU, Jin-Ming CHEN
  • Patent number: 10331046
    Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Ming Chang
  • Publication number: 20190163051
    Abstract: A method for forming a photomask is provided. The method includes forming a light blocking layer over a transparent substrate. The method includes forming a mask layer over the light blocking layer. The mask layer covers a first portion of the light blocking layer, and the first portion is over a second portion of the transparent substrate. The method includes removing the light blocking layer, which is not covered by the mask layer. The method includes removing the mask layer. The first portion of the light blocking layer is removed during removing the mask layer. The method includes removing the second portion of the transparent substrate to form a first recess in the transparent substrate. The method includes forming a first light blocking structure in the first recess.
    Type: Application
    Filed: July 26, 2018
    Publication date: May 30, 2019
    Inventors: Shih-Ming CHANG, Minfeng CHEN, Min-An YANG, Shao-Chi WEI
  • Publication number: 20190157085
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The first layer has a trench. The method includes forming first spacers over inner walls of the trench. The method includes removing a portion of the first spacers. The method includes forming a filling layer into the trench to cover the first spacers. The filling layer and the first spacers together form a strip structure. The method includes removing the first layer. The method includes forming second spacers over two opposite first sidewalls of the strip structure. The method includes forming third spacers over second sidewalls of the second spacers. The method includes removing the filling layer and the second spacers.
    Type: Application
    Filed: October 2, 2018
    Publication date: May 23, 2019
    Inventors: Chih-Ming LAI, Shih-Ming CHANG, Wei-Liang LIN, Chin-Yuan TSENG, Ru-Gun LIU
  • Publication number: 20190146361
    Abstract: A lithography apparatus is provided. The lithography apparatus includes an exposure system and a fluid handling system. The exposure system is configured to expose an exposure area on a substrate with an energy flow. The fluid handling system is configured to provide a heat transfer fluid flowing through a non-exposure area other than the exposure area on the substrate, to take heat away from the substrate.
    Type: Application
    Filed: June 13, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Ming CHANG
  • Publication number: 20190148162
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventor: Shih-Ming Chang
  • Publication number: 20190146355
    Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.
    Type: Application
    Filed: August 7, 2018
    Publication date: May 16, 2019
    Inventors: Dong-Yo Jheng, Ken-Hsien Hsieh, Shih-Ming Chang, Chih-Jie Lee, Shuo-Yen Chou, Ru-Gun Liu
  • Publication number: 20190148166
    Abstract: An interposer substrate is manufactured with a scribe line between adjacent regions. In an embodiment a separate exposure reticle is utilized to pattern the scribe line. The exposure reticle to pattern the scribe line will create an exposure region which overlaps and overhangs the exposure regions utilized to form adjacent regions.
    Type: Application
    Filed: August 1, 2018
    Publication date: May 16, 2019
    Inventors: Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu, Wen-Jung Chuang, Chun-Che Chen, Jhih-Ming Lin, Chih-Ching Lin, Shih-Wen Huang, Chun Hua Chang, Tsung-Yang Hsieh
  • Publication number: 20190146362
    Abstract: A lithography system is provided. The lithography system includes a mask and an optical module. The optical module is configured to optically form an invisible pellicle over the mask to protect the mask from contaminant particles.
    Type: Application
    Filed: February 27, 2018
    Publication date: May 16, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiu-Hsiang CHEN, Shih-Ming CHANG, Chih-Jie LEE, Han-Wei WU, Yung-Sung YEN, Ru-Gun LIU
  • Publication number: 20190131291
    Abstract: Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.
    Type: Application
    Filed: December 14, 2018
    Publication date: May 2, 2019
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10276363
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20190121249
    Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventor: Shih-Ming Chang
  • Publication number: 20190096811
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 28, 2019
    Inventors: Pochun WANG, Ting-Wei CHIANG, Chin-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Yai-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG
  • Publication number: 20190067290
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu
  • Patent number: 10162275
    Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Ming Chang