Patents by Inventor Shih-Ming Chang

Shih-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190131291
    Abstract: Methods disclosed herein form semiconductor devices having minimum spacings that correlate with spacer widths. An exemplary method includes forming a target layer over a substrate, forming a patterning layer over the target layer, and etching the target layer using the patterning layer as an etch mask. The patterning layer includes a first pattern feature, a second pattern feature spaced a first distance (corresponding with a first width of a first spacer fabricated during a first spacer patterning process) from the first pattern feature, and a third pattern feature spaced a second distance (corresponding with a second width of a second spacer fabricated during a second spacer patterning process) from the first pattern feature and a third distance (corresponding with a third width of a third spacer formed during the second spacer patterning process) from the second pattern feature.
    Type: Application
    Filed: December 14, 2018
    Publication date: May 2, 2019
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10276363
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. The method includes providing a substrate and a patterning-target layer over the substrate; patterning the patterning-target layer to form a main pattern; forming a middle layer over the patterning-target layer and a hard mask layer over the middle layer; patterning the hard mask layer to form a first cut pattern; patterning the hard mask layer to form a second cut pattern, a combined cut pattern being formed in the hard mask layer as a union of the first cut pattern and the second cut pattern; transferring the combined cut pattern to the middle layer; etching the patterning-target layer using the middle layer as an etching mask to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting an intersection portion between main pattern and the combined cut pattern.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20190121249
    Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
    Type: Application
    Filed: December 17, 2018
    Publication date: April 25, 2019
    Inventor: Shih-Ming Chang
  • Publication number: 20190096811
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Application
    Filed: September 19, 2018
    Publication date: March 28, 2019
    Inventors: Pochun WANG, Ting-Wei CHIANG, Chin-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Yai-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG
  • Publication number: 20190067290
    Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Shih-Ming Chang, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu
  • Patent number: 10163652
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shih-Ming Chang
  • Patent number: 10162275
    Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Ming Chang
  • Patent number: 10163885
    Abstract: Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced a first distance from the first target feature, and the third target feature is spaced a second distance from the first target feature. The first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10153166
    Abstract: The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate, a patterning-target layer over the substrate, and a hard mask layer over the patterning-target layer; forming a first pattern in the hard mask layer; removing a trim portion from the first pattern in the hard mask layer to form a trimmed first pattern; forming a first resist layer over the hard mask layer; forming a main pattern in the first resist layer; and etching the patterning-target layer using the main pattern and the trimmed first pattern as etching mask elements to form a final pattern in the patterning-target layer. In some embodiments, the final pattern includes the main pattern subtracting a first overlapping portion between the main pattern and the trimmed first pattern.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ming-Feng Shieh, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau
  • Patent number: 10147093
    Abstract: The present disclosure provides a system and a method for cash flow verification by a third-party payment platform. The system includes a server and a client device. The client device includes a network device, a storage device and a processor. The storage device is configured to store a plurality of programmed instructions and establish a client database. The processor is configured to execute the programmed instructions to generate execution history data, wherein the execution history data comprises cash flow history data, which can be produced by a third-party platform. While the network device is incapable of connecting the server through the Internet, the processor stores the execution history data in the client database; while the network device is capable of connecting the server through the Internet, the processor transmits the execution history data to the server through the network device for verification, and the verification comprises cash flow verification.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 4, 2018
    Assignee: INTERNATIONAL GAMES SYSTEM CO., LTD.
    Inventors: Jia-Wei Yang, Shih-Ming Chang
  • Patent number: 10095116
    Abstract: Systems and methods are disclosed herein for enhancing lithography printability, and in particular, for enhancing image contrast. An exemplary method includes receiving an integrated circuit (IC) design layout and generating an exposure map based on the IC design layout. The IC design layout includes a target pattern to be formed on a workpiece, and the exposure map includes an exposure grid divided into dark pixels and bright pixels that combine to form the target pattern. The method further includes adjusting the exposure map to increase exposure dosage at edges of the target pattern. In some implementations, the adjusting includes locating an edge portion of the target pattern in the exposure map, where the edge portion has a corresponding bright pixel, and assigning exposure energy from at least one dark pixel to the corresponding bright pixel, thereby generating a modified exposure map.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Wen Lo
  • Patent number: 10083271
    Abstract: Provided is a method of fabricating a semiconductor device. An integrated circuit (IC) layout plan is obtained. The IC layout plan contains critical features and non-critical features. Locational information regarding a defect on a blank reticle is obtained. The blank reticle is a candidate reticle for being patterned with the IC layout plan. Based on the locational information regarding the defect and the IC layout plan, a determination is made that at some of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan, regardless of whether the IC layout plan is globally manipulated or not before being patterned onto the blank reticle. In response to the determination, selected local portions of the IC layout plan are re-arranged such that none of the critical features will intersect with the defect if the blank reticle is patterned with the IC layout plan.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chia-Hao Yu
  • Patent number: 10083270
    Abstract: Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Shuo-Yen Chou, Ru-Gun Liu
  • Publication number: 20180249678
    Abstract: An inverse animal feeder comprises a feeding device, a power controlling device and a tray. The feeding device comprises a cover plate and a feeding opening inside the cover plate. The power controlling device comprises a motor in a main frame, a power source and a controller for feeding automatically. The tray mounted below the power controlling device and in an outer frame, and the tray is driven by the motor. The outer frame has a plurality of through holes; the main frame is mounted between the cover plate and the outer frame; and the cover plate is connected to the main frame by holders. Additionally, the main frame has at least one fastening block and the outer frame has at least one fastening groove, so that the fastening groove is fastened to the fastening groove to connect the main frame and the outer frame.
    Type: Application
    Filed: March 6, 2017
    Publication date: September 6, 2018
    Inventors: SHIH-MING CHANG, JIN-JUN CAO
  • Patent number: 10032664
    Abstract: The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: July 24, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Chih-Ming Lai, Ming-Feng Shieh, Ru-Gun Liu, Tsai-Sheng Gau
  • Publication number: 20180197750
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 12, 2018
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20180181012
    Abstract: A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
    Type: Application
    Filed: February 19, 2018
    Publication date: June 28, 2018
    Inventor: Shih-Ming Chang
  • Patent number: 10001698
    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and a second main feature; determining that the first main feature includes has a curvilinear-based shaped; determining that the second main feature has a polygon-based shape; and mapping a first portion of the IC design layout that includes the first main feature onto a polar coordinate and mapping a second portion of the IC design layout that includes the second main feature on onto a Cartesian coordinate.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 19, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventor: Shih-Ming Chang
  • Publication number: 20180165397
    Abstract: Target optimization methods are disclosed herein for enhancing lithography printability. An exemplary method includes receiving an IC design layout for a target pattern, wherein the target pattern has a corresponding target contour; modifying the target pattern, wherein the modified target pattern has a corresponding modified target contour; and generating an optimized target pattern when the modified target contour achieves functionality of the target pattern as defined by a constraint layer. The method can further include defining a cost function based on the constraint layer, where the cost function correlates a spatial relationship between a contour of the target pattern and the constraint layer.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventors: Shih-Ming Chang, Ken-Hsien Hsieh, Shuo-Yen Chou, Ru-Gun Liu
  • Publication number: 20180164688
    Abstract: Systems and methods are disclosed herein for enhancing lithography printability, and in particular, for enhancing image contrast. An exemplary method includes receiving an integrated circuit (IC) design layout and generating an exposure map based on the IC design layout. The IC design layout includes a target pattern to be formed on a workpiece, and the exposure map includes an exposure grid divided into dark pixels and bright pixels that combine to form the target pattern. The method further includes adjusting the exposure map to increase exposure dosage at edges of the target pattern. In some implementations, the adjusting includes locating an edge portion of the target pattern in the exposure map, where the edge portion has a corresponding bright pixel, and assigning exposure energy from at least one dark pixel to the corresponding bright pixel, thereby generating a modified exposure map.
    Type: Application
    Filed: December 14, 2016
    Publication date: June 14, 2018
    Inventors: Shih-Ming Chang, Wen Lo