Patents by Inventor Shih-Ming Chen
Shih-Ming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11608823Abstract: A micro pump is disclosed and includes a fluid-converging plate, a valve membrane, a fluid-outlet plate and a pump core module. The fluid-converging plate includes an inner recess, a protruding portion and a fluid-converging aperture. The protruding portion is disposed at a center of the inner recess. The valve membrane includes a valve aperture. The protruding portion of the fluid-converging plate abuts against the valve aperture. A fluid-converging chamber is formed between the valve membrane and the fluid-converging plate. The fluid-outlet plate in a ring shape includes a fluid-outlet channel. The valve aperture is in fluid communication with the fluid-outlet channel. When the fluid is inhaled into the pump core module, the fluid flows to the fluid-converging chamber through the fluid-converging aperture and then pushes out the valve membrane to flow into the fluid-outlet channel of the fluid-outlet plate through the valve aperture. Thereby the fluid transportation is achieved.Type: GrantFiled: June 16, 2020Date of Patent: March 21, 2023Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee
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Patent number: 11600749Abstract: Disclosed is a light-emitting device comprising a light-emitting stack having a length, a width, a first semiconductor layer, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer, wherein the first semiconductor layer, the active layer, and the second semiconductor layer are stacked in a stacking direction. A first electrode is coupled to the first semiconductor layer and extended in a direction parallel to the stacking direction and a second electrode is coupled to the second semiconductor layer and extended in a direction parallel to the stacking direction. A dielectric layer is disposed between the first electrode and the second electrode.Type: GrantFiled: June 8, 2018Date of Patent: March 7, 2023Assignee: EPISTAR CORPORATIONInventors: Shih-I Chen, Wei-Yu Chen, Yi-Ming Chen, Ching-Pei Lin, Tsung-Xian Lee
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Publication number: 20230069734Abstract: A semiconductor device includes a semiconductor substrate, an interconnection layer and an inductor pattern. The interconnection layer is disposed on the semiconductor substrate. The inductor pattern is electrically connected to the interconnection layer. The inductor pattern includes a first conductive line joined with a first terminal, a second conductive line joined with a second terminal, and a plurality of conductive coils. The conductive coils are joining the first conductive line to the second conductive line, and includes an outer coil joined with the first conductive line, an inner coil joined with the second conductive line and the outer coil. The second conductive line is spaced apart from a first side of the inner coil in a first direction by distance Y, the second terminal is spaced apart from a second side of the inner coil in a second direction by distance X1, wherein X1>1.25Y.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Hsien Lai, Shih-Ming Chen, Han-Chang Hsieh
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Publication number: 20230063857Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Inventors: Chia-Wei Chen, Chih-Yu Hsu, Hui-Chi Chen, Shan-Mei Liao, Jian-Hao Chen, Cheng-Hao Hou, Huang-Chin Chen, Cheng Hong Yang, Shih-Hao Lin, Tsung-Da Lin, Da-Yuan Lee, Kuo-Feng Yu, Feng-Cheng Yang, Chi On Chui, Yen-Ming Chen
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Publication number: 20230063405Abstract: The present disclosure provides an optical module. The optical module includes an optical component disposed in or on a carrier and configured to receive a first light. The optical component is further configured to transmit a second light to a first portion of the carrier and transmit a third light to a second portion of the carrier.Type: ApplicationFiled: September 2, 2021Publication date: March 2, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shih-Chieh TANG, Lu-Ming LAI, Yu-Che HUANG, Ying-Chung CHEN
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Patent number: 11586115Abstract: A method of operating a semiconductor apparatus includes generating an electric field in peripheral areas of a first covering structure and a second covering structure; causing a photomask to move to a position between the first and second covering structures such that the photomask at least partially vertically overlaps the first and second covering structures and such that particles attached to the photomask are attracted to the first and second covering structures by the electric field; and irradiating the photomask with light through light transmission regions of the first and second covering structures.Type: GrantFiled: August 25, 2021Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Ming Chang, Chiu-Hsiang Chen, Ru-Gun Liu
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Publication number: 20230046028Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Inventors: Chia-Hao Pao, Chih-Chuan Yang, Shih-Hao Lin, Chih-Hsuan Chen, Kian-Long Lim, Chao-Yuan Chang, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang
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Patent number: 11581300Abstract: A method is disclosed, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, in which the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, in which the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.Type: GrantFiled: November 6, 2020Date of Patent: February 14, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun-Li Chen, Kam-Tou Sio, Shih-Wei Peng, Chun-Kuang Chen, Ru-Gun Liu
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Publication number: 20230014253Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, a gate structure extending on the fin in a second direction, and a seal layer located on the sidewall of the gate structure. A first peak carbon concentration is disposed in the seal layer. A first spacer layer is located on the seal layer. A second peak carbon concentration is disposed in the first spacer layer. A second spacer layer is located on the first spacer layer.Type: ApplicationFiled: August 2, 2021Publication date: January 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shi-You Liu, Shih-Cheng Chen, Chia-Wei Chang, Chia-Ming Kuo, Tsai-Yu Wen, Yu-Ren Wang
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Publication number: 20230011313Abstract: A long-distance speed control system for a brushless DC motor of a fan is provided. The long-distance speed control system includes a switch connected with a mains power supply, a switch circuit, a voltage detection module, a power cord, a processing unit, and a drive unit, which can control the multi-stage rotational speed of the motor. In the field of brushless DC motors for fans, there is no need to use analog-to-digital conversion chips between the mains power supply and the processor, having the advantages of low cost, environmental protection, and reduction of waste of earth resources. Besides, the switch, the switch circuit and the power cord can withstand the mains power supply, having the advantages of less signal attenuation and long-distance transmission.Type: ApplicationFiled: July 9, 2021Publication date: January 12, 2023Inventor: Shih-Ming Chen
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Publication number: 20230008614Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.Type: ApplicationFiled: July 28, 2022Publication date: January 12, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chu-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
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Patent number: 11540368Abstract: A color temperature and brightness control system for an LED lamp of a ceiling fan includes a switch, a detection module, a determining module, a memory module, a control module, and a drive unit. The detection module detects the actuation of the switch, and the determining module performs a comparison. The control module outputs a control signal to the drive unit according to the calculation result of the determining module and the memory module to drive the lamp to actuate. The color temperature and brightness control system is able to control the lamp to be turned on/off and the brightness and color temperature of the lamp through a single switch.Type: GrantFiled: September 20, 2021Date of Patent: December 27, 2022Assignee: AIR COOL INDUSTRIAL CO., LTD.Inventor: Shih-Ming Chen
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Patent number: 11526081Abstract: An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.Type: GrantFiled: July 2, 2021Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Ming Chang, Wen Lo, Chun-Hung Liu, Chia-Hua Chang, Hsin-Wei Wu, Ta-Wei Ou, Chien-Chih Chen, Chien-Cheng Chen
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Patent number: 11519107Abstract: A fiber spreading apparatus which is configured to spread a carbon fiber bundle, and includes a feeding roll, a winding roll, a vibrating roller, and a first nozzle. The vibrating roller is disposed between the feeding roll and the winding roll, and is in contact with the carbon fiber bundle. The vibrating roller is rotated according to an axis of rotation, and is vibrated along a vibrating direction perpendicular to the axis of rotation. The first nozzle is disposed between the vibrating roller and the winding roll, and blows the carbon fiber bundle.Type: GrantFiled: December 30, 2019Date of Patent: December 6, 2022Assignee: Industrial Technology Research InstituteInventors: Chih-Kang Peng, Shih-Ming Chen, Yu-Cheng Chen
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Publication number: 20220379433Abstract: Provided is a dressing device for a carrier. The dressing device comprises a dresser, a swing arm, a base and at least one damper. A first end and a second end of the swing arm are coupled to the dresser and the base, respectively, and the at least one damper is disposed inside the swing arm. Any axial vibration of the dresser or the swing arm during dressing for the carrier can be compensated or attenuated by the damper in an active manner properly, so as to make the surface of the carrier flatter and more uniform, which not only improves a removal rate of material and a polishing result of the surface in the subsequent chemical mechanical planarization process, but also prolongs the service life of the carrier. The present disclosure further relates to a polishing system for dressing the carrier by using the said dressing device.Type: ApplicationFiled: May 26, 2022Publication date: December 1, 2022Inventors: Chao-Chang Chen, Jen-Chieh Li, Cheng-Hsi Chuang, Shih-Chung Hsu, Yu-Tung Tsai, Hsien-Ming Lee, Chun-Chen Chen, Ching-Tang Hsueh
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Publication number: 20220384590Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.Type: ApplicationFiled: May 26, 2021Publication date: December 1, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20220384454Abstract: A transistor includes a gate structure that has a first gate dielectric layer and a second gate dielectric layer. The first gate dielectric layer is disposed over the substrate. The first gate dielectric layer contains a first type of dielectric material that has a first dielectric constant. The second gate dielectric layer is disposed over the first gate dielectric layer. The second gate dielectric layer contains a second type of dielectric material that has a second dielectric constant. The second dielectric constant is greater than the first dielectric constant. The first dielectric constant and the second dielectric constant are each greater than a dielectric constant of silicon oxide.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Chih-Yu Hsu, Jian-Hao Chen, Chia-Wei Chen, Shan-Mei Liao, Hui-Chi Chen, Yu-Chia Liang, Shih-Hao Lin, Kuei-Lun Lin, Kuo-Feng Yu, Feng-Cheng Yang, Yen-Ming Chen
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Publication number: 20220376405Abstract: An antenna array device and an antenna unit thereof are provided. The antenna unit includes an antenna structure and a molding support. The antenna structure includes a substrate and a plurality of patches that are formed on the substrate. The substrate has a plurality of channel holes penetrating there-through. The molding support is integrally formed on the substrate as a single one-piece structure. The molding support has a first stand, a second stand, and a plurality of connection portions that are formed in the channel holes to connect the first stand and the second stand. The first stand and the second stand are formed on two sides of the substrate, respectively.Type: ApplicationFiled: October 14, 2021Publication date: November 24, 2022Inventors: SHIH-HONG CHEN, CHIEN-MING PENG, CHAO-CHUN LIN, YU-FU KUO
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Publication number: 20220376079Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
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Patent number: 11510295Abstract: A color temperature control device for an LED lamp is disclosed. The color temperature control device is electrically connected to a lamp and comprises a power supply and a power control circuit. The processor can output a color temperature change processing signal. The power control circuit can control the lamp to change the color temperature in a full-on state according to the full-on state of the lamp and a color temperature change processing signal. The power control circuit can control the lamp to change the color temperature in a dimming state according to the dimming state of the lamp and a color temperature change processing signal. Thereby, the color temperature of the lamp can be changed in the full-on state of the lamp or in the dimming state of the lamp, thereby increasing the convenience of use.Type: GrantFiled: December 6, 2021Date of Patent: November 22, 2022Assignee: AIR COOL INDUSTRIAL CO., LTD.Inventor: Shih-Ming Chen