Abstract: A semiconductor device includes a semiconductor substrate, an interconnection layer and an inductor pattern. The interconnection layer is disposed on the semiconductor substrate. The inductor pattern is electrically connected to the interconnection layer. The inductor pattern includes a first conductive line joined with a first terminal, a second conductive line joined with a second terminal, and a plurality of conductive coils. The conductive coils are joining the first conductive line to the second conductive line, and includes an outer coil joined with the first conductive line, an inner coil joined with the second conductive line and the outer coil. The second conductive line is spaced apart from a first side of the inner coil in a first direction by distance Y, the second terminal is spaced apart from a second side of the inner coil in a second direction by distance X1, wherein X1>1.25Y.

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

Abstract: A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.

Abstract: A Schottky diode includes a substrate with an epitaxy layer on which a cathode region and an anode region are defined. A cathode structure and an anode structure are formed in the cathode region and the anode region respectively and horizontally separated by a distance. The anode structure includes a plurality of p-type doped regions diffused from the epitaxy layer toward the substrate, with an interval is formed between adjacent two p-type doped regions. A backside metal film and a backside protection layer are sequentially formed on a back surface of the substrate. Since the manufacturing of the Schottky diode does not involve wire bonding and molding processes, the overall thickness of the Schottky diode is reduced and heat dissipation is improved. With the backside metal film on the back side of the substrate, an equivalent resistance and a forward voltage of the Schottky diode can be reduced.

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

Abstract: A liquid-cooling heat dissipation device includes a substrate, a fin assembly, a shell and a shunt component. The fin assembly is disposed on the substrate and has a plurality of channels parallelly arranged, and each of the channels has an inlet and an outlet opposite to each other. The shell is disposed on the substrate and has a liquid input port, a chamber is jointly formed by the shell and the substrate, and the chamber is located between the liquid input port and each of the inlets. The shunt component is disposed in the shell and has a plurality of manifold passages, the liquid input port is in communication with the chamber and each of the inlets through each of the manifold passages. Accordingly, the amount of fin member is increased in a fixed space to increase the heat dissipating efficiency.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first fin and a gate electrode. The first fin extends along a first direction. The gate electrode has a sidewall extending along a second direction different from the first direction. The sidewall of the gate electrode defines an indentation adjacent to the first fin in a top view.

Abstract: A liquid-cooling heat sink includes a substrate, a fin assembly, and a housing. The substrate has a longitudinal direction. The fin assembly is arranged on the substrate and includes multiple fins arranged at interval to form flow channels along the longitudinal direction. Each flow channel includes an inlet and an outlet opposite to each other. A turbulence structure divides a cross-section of at least one of the flow channels into at least two diverging passages. The housing arranged on the substrate covers the inlets and includes an inlet port and a chamber. Accordingly, the number of fins may be increased in a fixed space, and each flow channel has a smaller cross-sectional area to increase flow velocity of a dielectric liquid. Moreover, this reduces the flow resistance of the dielectric liquid in a turbulent flow area in each flow channel to improve the heat dissipation efficiency.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: An automatic processing device for liquid samples includes a sample region, a control module, an image identification device and a centrifuge. The sample region is configured to accommodate a plurality of centrifuge tubes. The control module includes a mechanical module. The mechanical module is configured to unscrew or tighten upper caps of the centrifuge tubes, and is configured to draw liquid from the centrifuge tubes or discharge liquid to the centrifuge tubes. The image identification device is coupled to the control module. The centrifuge is coupled to the control module. The centrifuge is configured to accommodate the centrifuge tubes and perform centrifugal treatment.

Abstract: Techniques pertaining to power saving by data throughput pattern prediction in wireless communications are described. A user equipment (UE) determines whether a probability of a first value being greater than a second value is higher than a threshold. The UE triggers a radio resource control (RRC) connection release with a network responsive to the probability being higher than the threshold. The first value represents a succeeding continuous duration of no uplink (UL) and downlink (DL) data. The second value represents an RRC inactivity timer duration plus a threshold duration.

Abstract: A sidewall protection layer is formed on sidewall spacers of a dummy gate structure of a semiconductor device prior to etching an underlying fin structure to form a source/drain recess. The sidewall protection layer enables the profile of the source/drain recess to be precisely controlled so that etching into residual dummy gate material near the source/drain recess is minimized or prevented. The sidewall protection layer may be removed or retained in the semiconductor device after formation of the source/drain recess. The sidewall protection layer reduces the likelihood of the source/drain regions of the semiconductor device contacting the metal gate structures of the semiconductor device after the dummy gate structures are replaced with the metal gate structures. Thus, the sidewall protection layer reduces the likelihood of electrical shorting between the source/drain regions and the metal gate structures.

Abstract: SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a ? ratio of an SRAM cell.

Abstract: A method for forming a thin film resistor with improved thermal stability is disclosed. A substrate having thereon a first dielectric layer is provided. A resistive material layer is deposited on the first dielectric layer. A capping layer is deposited on the resistive material layer. The resistive material layer is then subjected to a thermal treatment at a pre-selected temperature higher than 350 degrees Celsius in a hydrogen or deuterium atmosphere. The capping layer and the resistive material layer are patterned to form a thin film resistor on the first dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate, an interconnection layer and an inductor pattern. The interconnection layer is disposed on the semiconductor substrate. The inductor pattern is electrically connected to the interconnection layer. The inductor pattern includes a first conductive line joined with a first terminal, a second conductive line joined with a second terminal, and a plurality of conductive coils. The conductive coils are joining the first conductive line to the second conductive line, and includes an outer coil joined with the first conductive line, an inner coil joined with the second conductive line and the outer coil. The second conductive line is spaced apart from a first side of the inner coil in a first direction by distance Y, the second terminal is spaced apart from a second side of the inner coil in a second direction by distance X1, wherein X1>1.25Y.

Abstract: A ceiling fan infrared detection and control system has a wall-mounted controller, a ceiling fan controller, and a motor. The wall-mounted controller has an infrared sensor that is arranged outwardly and horizontally. The wall-mounted controller is pivotally equipped with a lens outside the infrared sensor for detecting infrared rays of a human body within a detection range. The control unit can output a wireless signal to the ceiling fan controller to control the motor according to the infrared detection result. The ceiling fan infrared detection and control system uses the technical feature that the lens is rotatable relative to the wall-mounted controller, so that the detection range can be moved synchronously along with the lens. The detection range has directivity and the function of adjusting the detection position, which can avoid false detection of a pet below the height of the detection range.

Abstract: A semiconductor device includes a semiconductor substrate, an interconnection layer and an inductor pattern. The interconnection layer is disposed on the semiconductor substrate. The inductor pattern is electrically connected to the interconnection layer. The inductor pattern includes a first conductive line joined with a first terminal, a second conductive line joined with a second terminal, and a plurality of conductive coils. The conductive coils are joining the first conductive line to the second conductive line, and includes an outer coil joined with the first conductive line, an inner coil joined with the second conductive line and the outer coil. The second conductive line is spaced apart from a first side of the inner coil in a first direction by distance Y, the second terminal is spaced apart from a second side of the inner coil in a second direction by distance X1, wherein X1>1.25Y.

Abstract: A brushless DC motor control system for a ceiling fan is electrically connected to a brushless DC motor, and includes a first switch, a detection module, a timer, a processing module, and a driving module. The first switch sends a first switch signal to the detection module for detection. The detection module outputs an operating electric potential detection signal to the timer. The timer outputs an operating electric potential timing signal to the processing module, so that the processing module outputs a first control signal and a second control signal to the driving module for controlling the brushless DC motor to change the rotational speed and the rotational direction respectively, increasing the convenience of use.

Abstract: A ceiling fan infrared detection and control system has a wall-mounted controller, a ceiling fan controller, and a motor. The wall-mounted controller has an infrared sensor that is arranged outwardly and horizontally. The wall-mounted controller is pivotally equipped with a lens outside the infrared sensor for detecting infrared rays of a human body within a detection range. The control unit can output a wireless signal to the ceiling fan controller to control the motor according to the infrared detection result. The ceiling fan infrared detection and control system uses the technical feature that the lens is rotatable relative to the wall-mounted controller, so that the detection range can be moved synchronously along with the lens. The detection range has directivity and the function of adjusting the detection position, which can avoid false detection of a pet below the height of the detection range.

Abstract: A brushless DC motor control system for a ceiling fan is electrically connected to a brushless DC motor, and includes a first switch, a detection module, a timer, a processing module, and a driving module. The first switch sends a first switch signal to the detection module for detection. The detection module outputs an operating electric potential detection signal to the timer. The timer outputs an operating electric potential timing signal to the processing module, so that the processing module outputs a first control signal and a second control signal to the driving module for controlling the brushless DC motor to change the rotational speed and the rotational direction respectively, increasing the convenience of use.