Abstract: A display includes a backlight module having elongated lamps. At least a pair of the lamps has a first lamp and a second lamp that are electrically connected in series. The first lamp and the second lamp are spaced apart with at least a third lamp positioned between the first and second lamps.

Abstract: An optical film with super low retardation, including metal oxide nano-particles dispersed in a transparent resin having a three-dimensional crosslinking structure. The optical film has about 0-2 nm in-plane retardation (Ro) and almost zero out-of-plane retardation (Rth). The optical film can replace conventional triacetyl cellulose (TAC) as a polarizer protective film to improve black-white contrast and color shift on liquid crystal displays at wide viewing angles.

Abstract: The backlight module includes a first lamp, a second lamp, a circuit board and a driving circuit board. The circuit board includes chambers to be connected to the first lamp and the second lamp, and capacitors to stabilize a voltage across two ends of each of the first lamp and the second lamp. The driving circuit board includes an inverter for driving the first lamp and the second lamp via the circuit board.

Abstract: Methods for forming a bump on a semiconductor substrate, the substrate having a contact pad thereon, is provided. In one embodiment, the method comprises depositing a passivation layer over the substrate and the contact pad. The passivation layer is patterned and etched to form a plurality of openings in the passivation layer exposing portions of the contact pad. An under bump metallurgy (UBM) layer is deposited over the etched passivation layer and in the plurality of openings thereof to contact the contact pad. A photoresist layer is formed on the UBM layer and then patterned and etched to form at least one opening substantially overlying the contact pad. An electrically conductive material is deposited into the opening formed in the photoresist layer and overlying the UBM layer and aligned with the contact pad. A portion of the remaining photoresist layer is removed. The UBM layer is etched using the electrically conductive material as a mask.

Abstract: An antireflective transparent zeolite hardcoat and fabrication method thereof. The transparent zeolite hardcoat comprises a zeolite nanostructure made of zeolite nanocrystals vertically stacked into a porous structure on a substrate, wherein the porosity increases with structure height, thereby providing a smooth refractive index transition.

Abstract: Disclosed herein are intermediate and solder bump structures. In one embodiment, a structure comprises a primary solder column comprising primary solder material and configured to electrically contact a bonding pad on a semiconductor substrate. The structure also comprises at least one secondary solder column comprising secondary solder material in electrical contact with the primary solder column, the at least one secondary column having a height and volume less than a height and volume of the primary solder column. In such structures, the primary solder column is further configured to form a primary solder bump comprising the primary solder material and at least a portion of the secondary solder material through cohesion from the at least one secondary solder column when the intermediate structure undergoes a reflow process.

Abstract: A composite bipolar plate of polymer electrolyte membrane fuel cells (PEMFC) is prepared as follows: a) preparing a bulk molding compound (BMC) material containing a vinyl ester resin and a graphite powder, the graphite powder content of BMC material ranging from 60 wt % to 80 wt %, based on the compounded mixture; b) molding the BMC material from step a) to form a bipolar plate having a desired shape at 80–200° C. and 500–4000 psi, wherein the graphite powder is of 40 mesh–80 mesh.

Abstract: A method of real-time monitoring the variation of dye solution in the process of a polarizer is provided that an ion chromatography is utilized to measure the variation of a reduction in the dye solution and analyze the components therein; moreover, an ion meter is utilized to measure the concentration of the dye solution.

Abstract: A polarizing substrate is placed into a dyeing tank for dyeing. A concentration of a dyeing agent in the dyeing tank is less than 800 ppm, and a dyeing period is greater than 200 seconds, so as to improve the dyeing of the polarizing substrate by lengthening the dyeing period and reducing the dyeing agent concentration.

Abstract: A novel under-bump metallization (UBM) structure for providing electrical communication is described. The UBM structure includes a plurality of metallic layers, which are deposited onto a bonding pad of a semiconductor device, such as a semiconductor chip. The UBM structure may be provided as an interface between the bonding pad and a solder bump deposited over the UBM structure. In one example, the UBM structure includes layers of nickel and copper in which nickel is the upper layer in contact with the solder bump and copper is the lower layer in contact with the bonding pad. The nickel layer is formed to include a downwardly depending perimeter portion, which serves as a cover to the copper layer of the UBM structure. Accordingly, the copper layer is shielded from contact with the solder material during the reflow process, thereby avoiding undesirable reactions between the copper and solder.

Abstract: A FLASH memory device comprising a substrate having a gate conductor formed thereover is provided. The gate conductor comprises a gate with a floating gate oxide layer formed thereon, the floating gate oxide layer including respective lateral tip portions, whereby the forward tunneling voltage of the FLASH memory is improved. In one embodiment, the respective tip portions have an average width of greater than or equal to about 250 ?.

Abstract: A protective film for a polarizer. An exemplary polarizer protective film includes a transparent resin with nanoscale particles dispersed therein, having an average diameter not exceeding 50 nanometers.

Abstract: A media-broadcasting device having USB slots is described. The media-broadcasting device connects to a USB-based memory device through the USB slot and has a main controller connected to the memory device through the USB slot for access to digital data stored in the memory device, an interior memory buffer connected to the main controller for temporarily storing the digital data under the command of the main controller, and an MP3 module connected to the main controller for retrieving and processing the digital data through the main controller.

Abstract: A floating gate structure and a method for forming a floating gate oxide layer comprising the following steps. A structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer.

Abstract: Disclosed herein are a method of manufacturing a solder bump on a semiconductor device, a solder bump structure formed on a substrate, and an intermediate solder bump structure. In one embodiment, the method includes creating a bonding pad over a semiconductor substrate, and placing a mask layer over the substrate and the bonding pad. The method also includes forming an opening in the mask layer having a primary solder mold and at least one secondary solder mold joined with the primary mold, where the opening exposes a portion of the bonding pad. In this embodiment, the method further includes filling the primary solder mold and the at least one secondary solder mold with solder material to form corresponding primary and at least one secondary solder columns in electrical contact with the bonding pad. The method also includes removing the mask layer after the filling of the solder molds with the solder material.

Abstract: The invention relates to a lamp frequency control system for a display and method for controlling the lamp frequency. The lamp frequency control system comprises a driving control device and a lamp frequency control device. The driving control device has a driving mode selector for selecting a driving mode from at least two driving modes. According to the selected driving mode, the driving mode selector outputs at least one corresponding frequency control signal. According to the corresponding frequency control signal, the lamp frequency control device obtains at least one corresponding lamp frequency. According to the various driving mode, the lamp frequency control system of the invention obtains the corresponding lamp frequency. That is, the lamp frequency can be adjusted to match the driving mode. Therefore, the lamp frequency can be adjusted at a frequency section without the water flow interference. The lamp frequency control system of the invention can resolve the water flow interference.

Abstract: A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.

Abstract: A floating gate structure and a method for forming a floating gate oxide layer comprising the following steps. A structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer.

Abstract: A gate process and a gate process for an embedded memory device. A semiconductor silicon substrate has a memory cell area and a logic circuit area. A first dielectric layer is formed overlying the semiconductor silicon substrate, and then a gate structure is formed overlying the first dielectric layer of the memory cell area. Next, a protective layer is formed overlying the first dielectric layer and the top and sidewall of the gate structure. Next, an insulating spacer is formed overlying the protective layer disposed overlying the sidewall of the gate structure. Next, a pre-cleaning process is performed to remove the protective layer and the first dielectric layer overlying the logic circuit area. Next, a second dielectric layer is formed overlying the logic circuit area, and then a gate layer is formed overlying the second dielectric layer of the logic circuit area.

Abstract: A floating gate structure and a method for forming a floating gate oxide layer comprising the following steps. A structure having a first dielectric layer formed thereover is provided. An oxide layer is formed over the first dielectric layer. A nitride layer is formed over the oxide layer. The nitride layer is patterned to form an opening exposing a portion of the oxide layer. A portion of the first dielectric layer is exposed by removing: the exposed portion of the oxide layer; and portions of the oxide layer underneath the patterned nitride layer adjacent to the opening to form respective undercuts. The exposed portion of the first dielectric layer is oxidized to form the floating gate oxide layer.