Patents by Inventor Shih-Ting Lin

Shih-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180337137
    Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 22, 2018
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
  • Publication number: 20180337065
    Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Jing-Cheng Lin, Shih Ting Lin, Chen-Hua Yu
  • Publication number: 20180188115
    Abstract: A MEMS apparatus having measuring range selector including a sensor and an IC chip is provided. The sensor includes a sensing device. The IC chip includes a voltage range selector, an analog front end, a control device and an A/D converter. The sensing device is configured to detect the physical quantity and generate a sensing voltage. The voltage range selector is configured to select a sub-voltage range having a first upper-bound and a first lower-bound. The analog front end is configured to receive the sensing voltage and output a first voltage. The A/D converter has a full scale voltage range having a second lower-bound and a second upper-bound. A ratio of the full scale voltage range to the sub-voltage range is defined as a gain factor. A difference obtained by subtracting the first lower-bound from the first voltage is defined as a shift factor. The control device is configured to adjust the first voltage to the second voltage according to the gain factor and the shift factor.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 5, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Yu-Wen Hsu, Feng-Chia Hsu, Chao-Ta Huang, Shih-Ting Lin
  • Publication number: 20180117710
    Abstract: Disclosed is a laser system and a laser flare machining method. The laser system includes a laser light source, a splitter element, and a scanning lens assembly. The laser light source projects a first light beam. The splitter element is furnished on a first path along which the first light beam travels, and splits the first light beam into a second light beam traveling along a second path and a third light beam traveling along a third path. The scanning lens assembly is furnished on the second path and the third path, and focus the second light beam and the third light beam at a machining position to process a work piece.
    Type: Application
    Filed: December 22, 2016
    Publication date: May 3, 2018
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shih-Ting LIN, Ying-Tso LIN, Hong-Xi TSAU
  • Publication number: 20180096976
    Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.
    Type: Application
    Filed: November 15, 2017
    Publication date: April 5, 2018
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih Ting Lin, Shin-Puu Jeng
  • Patent number: 9847315
    Abstract: Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a second region opposite the first region. The first region comprises a first width, and the second region comprises a second width. The second width is greater than the first width.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ting Lin, Szu Wei Lu, Jui-Pin Hung, Jing-Cheng Lin
  • Publication number: 20170352626
    Abstract: A method of forming a package assembly includes forming a first dielectric layer over a carrier substrate; forming a conductive through-via over the first dielectric layer; treating the conductive through-via with a first chemical, thereby roughening surfaces of the conductive through-via; and molding a device die and the conductive through-via in a molding material.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 9831224
    Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih Ting Lin, Shin-Puu Jeng
  • Patent number: 9793187
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ting Lin, Kung-Chen Yeh, Szu-Wei Lu, Jing-Cheng Lin
  • Publication number: 20170125374
    Abstract: A rework process includes attaching a first bond head to a first semiconductor package. The contact pads of the first semiconductor package are bonded to contact pads of a second semiconductor package by solder joints. The rework process further includes performing a first local heating process to melt the solder joints, removing the first semiconductor package using the first bond head, and removing at least a portion of solder from the contact pads of the second semiconductor package.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Inventors: Shih Ting Lin, Justin Huang, Tsung-Fu Tsai, Jing-Cheng Lin, Chen-Hua Yu
  • Patent number: 9514988
    Abstract: Packaged semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a method of packaging semiconductor devices comprises attaching a first substrate to a film. A first portion of the film is attached to a first region of the first substrate and a second portion of the film is attached to a second region of the first substrate. The method further comprises separating the first portion of the film from the second portion of the film.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: December 6, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ting Lin, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 9502271
    Abstract: Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shih Ting Lin, Jing-Cheng Lin, Shang-Yun Hou, Szu Wei Lu
  • Patent number: 9418876
    Abstract: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: August 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Weng-Jin Wu, Shih Ting Lin, Cheng-Lin Huang, Szu Wei Lu, Shin-Puu Jeng, Chen-Hua Yu
  • Patent number: 9412662
    Abstract: A semiconductor structure and a method of manufacture are provided. Devices, such as integrated circuit dies, are mounted on a substrate, such as another die, packaging substrate, interposer, or the like, and recesses are formed in the substrate along the scribe lines. One or more molding compound layers are formed in the recesses and between adjacent dies. A backside thinning process may be performed to expose the molding compound in the recesses. A singulation process is performed in the molding compound layer in the recesses. In an embodiment, a first molding compound layer is formed in the recess, and a second molding compound is formed over the first molding compound layer and between adjacent dies. The devices may be placed on the substrate before or after forming the recesses.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Ting Lin, Jing-Cheng Lin, Szu-Wei Lu
  • Patent number: 9382112
    Abstract: A method for manufacturing a MEMS device includes the following operations. An SOI wafer including a device layer, an insulating layer and a handle layer is provided. The device layer is etched to form a recess and an annular protrusion surrounding the recess. A moving part and a spring of the MEMS device are formed on the recess by etching the device layer, the insulating layer and the handle layer. An anchor of the MEMS device is formed at the annular protrusion by etching the device layer, the insulating layer and the handle layer. The moving part and the anchor are connected to each other by the spring. The insulating layer is disposed between a first conductive portion and a second conductive portion of the moving part. The insulating layer is disposed between a first conductive portion and a second conductive portion of the anchor.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: July 5, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu Wen Hsu, Shih Ting Lin, Jen Yi Chen, Chao Ta Huang
  • Publication number: 20160181231
    Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.
    Type: Application
    Filed: February 26, 2016
    Publication date: June 23, 2016
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih Ting Lin, Shin-Puu Jeng
  • Patent number: 9281297
    Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu Wei Lu, Shih Ting Lin, Shin-Puu Jeng
  • Patent number: 9227841
    Abstract: One embodiment discloses an apparatus integrating a microelectromechanical system device with a circuit chip which includes a circuit chip, a microelectromechanical system device, a sealing ring, and a lid. The circuit chip comprises a substrate and a plurality of metal bonding areas. The substrate has an active surface with electrical circuit area, and the metal bonding areas are disposed on the active surface and electrically connected to the electrical circuits. The microelectromechanical system device comprises a plurality of bases and at least one sensing element. The bases are connected to at least one of the metal bonding areas. The at least one sensing element is elastically connected to the bases. The sealing ring surrounds the bases, and is connected to at least one of the metal bonding areas. The lid is opposite to the active surface of the circuit chip, and is connected to the sealing ring to have a hermetic chamber which seals the sensing element and the active surface of the circuit chip.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: January 5, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao Ta Huang, Shih Ting Lin, Yu Wen Hsu
  • Publication number: 20150357255
    Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including bonding a die to a top surface of a first substrate, the die being electrically coupled to the first substrate, and forming a support structure on the top surface of the first substrate, the support structure being physically separated from the die with a top surface of the support structure being coplanar with a top surface of the die. The method further includes performing a sawing process on the first substrate, the sawing process sawing through the support structure.
    Type: Application
    Filed: August 17, 2015
    Publication date: December 10, 2015
    Inventors: Shih Ting Lin, Kung-Chen Yeh, Szu-Wei Lu, Jing-Cheng Lin
  • Publication number: 20150260593
    Abstract: The invention provides a micro-electro-mechanical system pressure sensor. The micro-electro-mechanical system pressure sensor includes: a substrate, including at least one conductive wiring; a membrane disposed above the substrate to form a semi-open chamber between the membrane and the substrate, the semi-open chamber having an opening to receive an external pressure; and a cap, disposed above the membrane and forming an enclosed space with the membrane, the cap including a top electrode corresponding to the membrane and at least one portion of the membrane forming a bottom electrode, wherein the top and bottom electrodes form a sensing capacitor to sense the external pressure.
    Type: Application
    Filed: July 11, 2014
    Publication date: September 17, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Yu-Wen Hsu, Chia-Yu Wu, Shih-Chieh Lin, Shih-Ting Lin