Patents by Inventor Shih-Wei Lin

Shih-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272585
    Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defined by a processing chamber, and a wafer chuck structure arranged within the processing chamber. The wafer chuck structure is configured to hold a wafer during a fabrication process. The wafer chuck includes a lower portion and an upper portion arranged over the lower portion. The lower portion includes trenches extending from a topmost surface towards a bottommost surface of the lower portion. The upper portion includes openings that are holes, extend completely through the upper portion, and directly overlie the trenches of the lower portion. Multiple of the openings directly overlie each trench. Further, cooling gas piping is coupled to the trenches of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas piping.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Jung Chen, Shih-Wei Lin, Lee-Chuan Tseng
  • Patent number: 12265262
    Abstract: Structures and methods including a waveguide having a cladding layer surrounding a core layer disposed over a substrate, a cavity extending into the substrate adjacent the waveguide, a fiber disposed in the cavity, and an isolation space extending into the substrate and disposed under the waveguide. A plurality of holes may extend through the cladding layer adjacent the core layer.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Shih-Wei Lin
  • Patent number: 12235689
    Abstract: A cable arrangement mechanism is provided, which is disposed inside the housing of an electronic device. The cable arrangement mechanism includes a first tube, a second tube, and a plurality of first resilient elements. The first tube includes a first base, a first extension connected to the first base and extending from a first inner surface, and a first extrusion connected to the first base and extending from a first outer surface. The second tube includes a second base, a second extension connected to the second base and extending from a second inner surface, and a second extrusion connected to the second base and extending from a second outer surface. The first resilient elements respectively connect the first extrusion and the second extrusion to the housing, so that the first tube and the second tube are rotatably connected to the housing.
    Type: Grant
    Filed: September 14, 2023
    Date of Patent: February 25, 2025
    Assignee: QUANTA COMPUTER INC.
    Inventors: Shih-Wei Lin, Chih-Cheng Chu, Jui Hsien Huang, Kuo-Huan Wei, Ping-Hou Lin
  • Publication number: 20250048753
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material. A second semiconductor material is disposed on the substrate. A doped region is between the substrate and a part of the second semiconductor material. The second semiconductor material includes a projection extending outward from a surface of the second semiconductor material and towards the photodiode region. The projection extends through the doped region.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 6, 2025
    Inventors: Yung-Chang Chang, Shih-Wei Lin, Te-Hsien Hsieh, Jung-I Lin
  • Patent number: 12183764
    Abstract: The present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed onto the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connecting to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. A bottom surface of the second semiconductor material region is directly over the photodiode region.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chang Chang, Shih-Wei Lin, Te-Hsien Hsieh, Jung-I Lin
  • Publication number: 20240379400
    Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defined by a processing chamber, and a wafer chuck structure arranged within the processing chamber. The wafer chuck structure is configured to hold a wafer during a fabrication process. The wafer chuck includes a lower portion and an upper portion arranged over the lower portion. The lower portion includes trenches extending from a topmost surface towards a bottommost surface of the lower portion. The upper portion includes openings that are holes, extend completely through the upper portion, and directly overlie the trenches of the lower portion. Multiple of the openings directly overlie each trench. Further, cooling gas piping is coupled to the trenches of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas piping.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Ting-Jung Chen, Shih-Wei Lin, Lee-Chuan Tseng
  • Publication number: 20240372018
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region disposed in a semiconductor substrate and a second doped region disposed in the semiconductor substrate. A photodetector is disposed between the first doped region and the second doped region. The photodetector has a lower surface that arcs between opposing sidewalls of the photodetector in a cross-sectional view. The first doped region and the second doped region contact the lower surface of the photodetector.
    Type: Application
    Filed: July 17, 2024
    Publication date: November 7, 2024
    Inventors: Chen-Hao Chiang, Shih-Wei Lin, Eugene I-Chun Chen, Yi-Chen Chen
  • Patent number: 12136679
    Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region having a first doping type disposed in a semiconductor substrate. A second doped region having a second doping type different than the first doping type is disposed in the semiconductor substrate and laterally spaced from the first doped region. A waveguide structure is disposed in the semiconductor substrate and laterally between the first doped region and the second doped region. A photodetector is disposed at least partially in the semiconductor substrate and laterally between the first doped region and the second doped region. The waveguide structure is configured to guide one or more photons into the photodetector. The photodetector has an upper surface that continuously arcs between opposite sidewalls of the photodetector. The photodetector has a lower surface that continuously arcs between the opposite sidewalls of the photodetector.
    Type: Grant
    Filed: May 3, 2023
    Date of Patent: November 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hao Chiang, Shih-Wei Lin, Eugene I-Chun Chen, Yi-Chen Chen
  • Publication number: 20240342229
    Abstract: The present disclosure relates to an anti-fatigue Lactobacillus composition. The anti-fatigue Lactobacillus composition, which includes at least one of Lactobacillus brevis GKEX, Lactobacillus plantarum GKK1 and Lactobacillus johnsonii GKJ2 as an active ingredient, administered to a healthy subject for a continuous period of time, can significantly improve fatigue-related biochemical indices and prolong aerobic exercise time to exhaustion, and thus can be used as an active ingredient for preparation of various compositions for anti-fatigue and/or improving athletic ability.
    Type: Application
    Filed: June 27, 2024
    Publication date: October 17, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, You-Shan TSAI, Tzu-Chun LIN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, Zi-He WU, Yen-Po CHEN
  • Publication number: 20240332061
    Abstract: Depositing an oxide material on sidewalls of trenches between etching cycles allows narrower trenches to be etched to increased depths without causing over-etching of wider trenches. As a result, efficiency of a device including the trenches (e.g., a silicon photonics (SiPh) device or a pixel device, among other examples) is increased. For example, because light leakage and light scattering is reduced in an SiPh device, power is conserved at a transmission device that can decrease transmit power on account of the increased efficiency.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Shih-Wei LIN, Hau-Yan LU, Te-Hsien HSIEH
  • Publication number: 20240291524
    Abstract: Techniques pertaining to trigger-based (TB) implicit feedback for implicit beamforming in wireless communications are described. An apparatus (e.g., an access point (AP)) triggers each of one or more stations (STAs) to transmit a respective feedback. The apparatus estimates a respective steering matrix with respect to each of the one or more STAs based on the respective feedback. The apparatus then transmits a respective steered data to each of the one or more STAs based on the respective steering matrix.
    Type: Application
    Filed: December 28, 2023
    Publication date: August 29, 2024
    Inventors: Cheng-En Hsieh, Ming-Hsiang Tseng, Kang-Li Wu, Shih-Wei Lin, Hao-Chih Yu, Ching-Yu Kuo, Hung-Tao Hsieh
  • Publication number: 20240256002
    Abstract: A cable arrangement mechanism is provided, which is disposed inside the housing of an electronic device. The cable arrangement mechanism includes a first tube, a second tube, and a plurality of first resilient elements. The first tube includes a first base, a first extension connected to the first base and extending from a first inner surface, and a first extrusion connected to the first base and extending from a first outer surface. The second tube includes a second base, a second extension connected to the second base and extending from a second inner surface, and a second extrusion connected to the second base and extending from a second outer surface. The first resilient elements respectively connect the first extrusion and the second extrusion to the housing, so that the first tube and the second tube are rotatably connected to the housing.
    Type: Application
    Filed: September 14, 2023
    Publication date: August 1, 2024
    Inventors: Shih-Wei LIN, Chih-Cheng CHU, Jui Hsien HUANG, Kuo-Huan WEI, Ping-Hou LIN
  • Patent number: 12043537
    Abstract: The present disclosure provides a method of manufacturing a MEMS device. In some embodiments, a first interlayer dielectric layer is formed over a substrate, and a diaphragm is formed over the first interlayer dielectric layer. Then, a second interlayer dielectric layer is formed over the diaphragm. A first etch is performed to form an opening through the second interlayer dielectric layer and the diaphragm and reaching into an upper portion of the first interlayer dielectric layer. A second etch is performed to the first interlayer dielectric layer and the second interlayer dielectric layer to form recesses above and below the diaphragm and to respectively expose a portion of a top surface and a portion of a bottom surface of the diaphragm. A sidewall stopper is formed along a sidewall of the diaphragm into the recesses of the first interlayer dielectric layer and the second interlayer dielectric layer.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Lin, Chang-Ming Wu, Ting-Jung Chen
  • Publication number: 20240210624
    Abstract: A semiconductor device is provided. The semiconductor device includes a waveguide over a substrate. The semiconductor device includes a first dielectric structure over the substrate, wherein a portion of the waveguide is in the first dielectric structure. The semiconductor device includes a second dielectric structure under the waveguide, wherein a first sidewall of the second dielectric structure is adjacent a first sidewall of the substrate.
    Type: Application
    Filed: March 4, 2024
    Publication date: June 27, 2024
    Inventors: Yi-Chen CHEN, Lee-Chuan TSENG, Shih-Wei LIN
  • Publication number: 20240198451
    Abstract: A fiber output hybrid laser system, which having at least a blue ray laser model, emitting a blue ray laser beam; an infrared optic fiber laser module, emitting an infrared laser beam; a fiber bundle combining the above mentioned two laser beams, an output optical assembly collimating the laser beams, and generating focal points of two wavelengths; wherein the blue ray laser beam and the infrared laser beam which are coaxial and coincident to emit light, and the BPP of the blue ray laser beam and the infrared laser beam are both less than 10 mm*mrad; the power of the blue ray laser beam is between 20˜100 W, the power of the infrared laser beam is between 500˜5000 W, so as to obtain the best welding and cladding effects.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Inventors: CHI LUEN WANG, HUNG SHENG LEE, YI SHIN SU, SHIH WEI LIN, SZUTSUN SIMON OU
  • Patent number: 12006208
    Abstract: A semiconductor oxide plate is formed on a recessed surface in a semiconductor matrix material layer. Comb structures are formed in the semiconductor matrix material layer. The comb structures include a pair of inner comb structures spaced apart by a first semiconductor portion. A second semiconductor portion that laterally surrounds the first semiconductor portion is removed selective to the comb structures using an isotropic etch process. The first semiconductor portion is protected from an etchant of the isotropic etch process by the semiconductor oxide plate, the pair of inner comb structures, and a patterned etch mask layer that covers the comb structures. A movable structure for a MEMS device is formed, which includes a combination of the first portion of the semiconductor matrix material layer and the pair of inner comb structures.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ting-Jung Chen, Shih-Wei Lin
  • Publication number: 20240139262
    Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
  • Patent number: 11921325
    Abstract: A semiconductor device is provided. The semiconductor device includes a waveguide over a substrate. The semiconductor device includes a first dielectric structure over the substrate, wherein a portion of the waveguide is in the first dielectric structure. The semiconductor device includes a second dielectric structure under the waveguide, wherein a first sidewall of the second dielectric structure is adjacent a first sidewall of the substrate.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Chen Chen, Lee-Chuan Tseng, Shih-Wei Lin
  • Patent number: 11904917
    Abstract: An anti-collision control method and a rail vehicle control system are provided. The rail vehicle control system includes a control apparatus configured to implement the anti-collision control method to prevent a plurality of vehicles on a plurality of rails from colliding with each other. The anti-collision control method includes receiving a transfer requirement data to decide which one of the vehicles and which one of the rails are respectively an assigned vehicle and an assigned rail; planning a movement path and a movement space according to the transfer requirement data and a vehicle dimension data; determining whether any portion of the movement space is reserved; and in response to the movement space being reserved, the assigned vehicle is controlled to not move, or the movement space is reserved and the assigned vehicle is controlled to move according to the movement path along the assigned rail.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: February 20, 2024
    Assignee: MIRLE AUTOMATION CORPORATION
    Inventors: Shih-Wei Lin, Hsing-Lu Huang, Wun-Jian Wei
  • Patent number: 11888285
    Abstract: A low numerical aperture fiber output diode laser module, which having several independent diode lasers, and collimated and converged the light beam, for the coupling the light to the core optical fiber with a core diameter of 105 um and a numerical aperture of 0.12. Compared with general products with a numerical aperture of 0.22, the light output angle is reduced to 55%, and use a general blue laser diode for verification. Use an optical software for facilitating the design and optimization of the parameters of the optical lens module.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 30, 2024
    Assignee: Turning Point Lasers Corporation
    Inventors: Chi-Luen Wang, Hung-Sheng Lee, Tai-Ming Chang, Chun-Hui Yu, Yu-Ching Yeh, Sheng-Ping Lai, Shih-Wei Lin, Yuan-He Teng, Li-Chang Tsou, Szutsun Simon Ou