Abstract: A method includes forming a first protruding semiconductor fin and a dummy fin protruding higher than top surfaces of isolation regions. The first protruding semiconductor fin is parallel to the dummy fin, forming a gate stack on a first portion of the first protruding semiconductor fin and a second portion of the dummy fin. The method further includes recessing a third portion of the first protruding semiconductor fin to form a recess, recessing an fourth portion of the dummy fin to reduce a height of the fourth portion of the dummy fin, and forming an epitaxy semiconductor region in the recess. The epitaxy semiconductor region is grown toward the dummy fin.

Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.

Abstract: A rearview mirror with display function includes a display structure layer, a rearview mirror structure layer, a plastic frame and an electrochromic material. The display structure layer includes a first transparent substrate, a display body layer and a transflective layer on opposite sides of the first transparent substrate. The rearview mirror structure layer is disposed on one side of the display structure layer, and includes a second transparent substrate, a ring-shaped shielding layer, a touch sensing layer, an insulating substrate, and a transparent electrode layer. The ring-shaped shielding layer is disposed around a third surface of the second transparent substrate, and the touch sensing layer covers the third surface and the ring-shaped shielding layer. The ring-shaped shielding layer is electrically insulated from the touch sensing layer. The plastic frame, the transflective layer and the transparent electrode layer define an accommodating space.

Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.

Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

Abstract: A method, computer program, and computer system is provided for estimating three-dimensional hand poses in images. Data corresponding to two hand images is receive, and an optical flow value corresponding to a change in a hand gesture in the received hand image data is calculate. A heat map is generated based on the calculated optical flow, and a hand mesh map is estimated based on the generated heat map. A hand pose present within the hand images is determined based on the estimated hand mesh map.

Abstract: A method of generating an integrated circuit includes: placing a plurality of electronic components on a layout floor plan to generate a placing layout of the integrated circuit; forming a clock tree upon the placing layout to generate a synthesis layout of the integrated circuit; routing the synthesis layout to generate a routed layout of the integrated circuit; performing a DRC process upon the routed layout to obtain a layout region with a systematic DRC violation; generating a plurality of prediction gains of the layout region according to a plurality of placement recipes respectively; and generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe in the plurality of placement recipes.

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion-is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

Abstract: A circuit board component layout determination method includes the steps of: (1) simulating the placement of components by a circuit board layout software program; (2) performing a circuit board component layout density analysis to obtain a circuit board component layout density percentage; (3) determining whether or not the simulated placement of components is feasible according to the circuit board component layout density percentage, and if yes, carrying out step (4); and (4) placing the components into the circuit board. The method uses a circuit board layout software program and a spreadsheet or a database to calculate the statistics of an area of a circuit board that can be laid and an area of the circuit board that cannot be laid, so as to analyze and determine the implementability of a component layout, and improve the control, efficiency and cost-effective of the component layout of the circuit board.

Abstract: A computer-implemented method, computer readable storage medium, and computer system is provided for estimating three-dimensional (3D) hand poses in images by receiving data corresponding to a hand image, generating a depth map corresponding to the received hand image data, and estimating a hand pose from the received hand image data and the generated depth map.

Abstract: A method, computer program, and computer system is provided for receiving data corresponding to a tomograph scan associated with a patient, extracting slices from the received tomograph scan data, and determining adjacent slices for each of the extracted slices. The extracted slices and the adjacent slices may be grouped into slabs, and features associated with the slabs may be identified. It may be determined that a slab corresponding to the identified features contains a feature associated with ICH.

Abstract: An electrochromic mirror module including a light-transmissive substrate, an opaque touch sensing layer and an electrochromic device is provided. The light-transmissive substrate has a visible surface and a back surface disposed opposite to the visible surface. The opaque touch sensing layer and the electrochromic layer are disposed on the back surface. Distribution areas of the opaque touch sensing layer and the electrochromic layer are different on the back surface. An electrochromic mirror module including reflective layer and electrochromic device is also provided.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second gate dielectric of the first dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

Abstract: The present disclosure provides compounds with a hydrophilic self-immolative linker, which is cleavable under appropriate conditions and incorporates a hydrophilic group to provide better solubility of the compound. The compounds of the present disclosure comprise a drug moiety, a targeting moiety capable of targeting a selected cell population, and a linker which contains an acyl unit, an optional spacer unit for providing distance between the drug moiety and the targeting moiety, a peptide linker which can be cleavable under appropriate conditions, a hydrophilic self-immolative linker, and an optional second self-immolative spacer or cyclization self-elimination linker.