Abstract: A method of fabricating a semiconductor device is disclosed. The method includes providing a fin layer. Dummy gates are formed over the fin layer, where the dummy gates are formed to taper from a smaller width at a top region of the dummy gates to a larger width at a bottom region of the dummy gates. Sidewall spacers are formed on sidewalls of the dummy gates. An interlayer dielectric is formed in regions between the dummy gates and contacts the sidewall spacers. The dummy gates are removed to form openings in the interlayer dielectric and to expose the sidewall spacers on sides of the openings in the interlayer dielectric. The sidewall spacers are etched at a greater rate at a top region of the sidewall spacers than at a bottom region of the sidewall spacers.

Abstract: A touch display device includes a flexible substrate, a light emitting structure layer, and a flexible touch sensing layer. The flexible substrate has a first surface and a second surface opposite to each other. The light emitting structure layer is disposed on the first surface of the flexible substrate. The flexible touch sensing layer is disposed on the second surface of the flexible substrate.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: A rear-view mirror with a display function includes a rear-view mirror body and a display structure layer. The display structure layer is disposed on one side of the rear-view mirror body and includes a plurality of light-emitting diodes and a driving circuit layer. The light-emitting diodes are located between the rear-view mirror body and the driving circuit layer. The light-emitting diodes are electrically connected to the driving circuit layer.

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

Abstract: Provided herein are tetravalent antibodies that specifically bind to human PSGL-1. Unlike bivalent antibodies, these tetravalent antibodies contain a dimer of two monomers, with each monomer comprising two light chain variable (VL) domains and two heavy chain variable (VH) domains. This format allows for cross-linker/FcR-expressing cell-independent tetravalent antibodies against PSGL-1 that show enhanced efficacy as compared to bivalent PSGL-1 antibodies. These tetravalent antibodies can be used in a variety of diagnostic and therapeutic methods, including without limitation treating T-cell mediated inflammatory diseases, transplantations, and transfusions.

Abstract: A computer-implemented method of training a neural network for organ segmentation may be provided. The method may include: collecting a set of digital sample images from a database; inputting the collected set of digital images into a neural network recognition model; and training the neural network recognition model to recognize a first object in a first digital image as a specific object based on the first object being similar to a second object in a second digital image. The method may comprise predicting a signed distance map (SDM) in conjunction with a segmentation map.

Abstract: A method includes depositing a dummy gate dielectric layer over a semiconductor region, depositing a dummy gate electrode layer, and performing a first etching process. An upper portion of the dummy gate electrode layer is etched to form an upper portion of a dummy gate electrode. The method further includes forming a protection layer on sidewalls of the upper portion of the dummy gate electrode, and performing a second etching process. A lower portion of the dummy gate electrode layer is etched to form a lower portion of the dummy gate electrode. A third etching process is then performed to etch the lower portion of the dummy gate electrode using the protection layer as an etching mask. The dummy gate electrode is tapered by the third etching process. The protection layer is removed, and the dummy gate electrode is replaced with a replacement gate electrode.

Abstract: A semiconductor device includes a plurality of semiconductor layers vertically separated from one another. Each of the plurality of semiconductor layers extends along a first lateral direction. The semiconductor device includes a gate structure that extends along a second lateral direction and comprises at least a lower portion that wraps around each of the plurality of semiconductor layers. The lower portion of the gate structure comprises a plurality of first gate sections that are laterally aligned with the plurality of semiconductor layers, respectively, and wherein each of the plurality of first gate sections has ends that each extend along the second lateral direction and present a first curvature-based profile.

Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

Abstract: A method is provided in the present disclosure. The method includes several operations: generating a floor plan having multiple macros for an integrated circuit; adjusting the macros according to a channel area interposed between the pins; separating the macros by a channel width of the channel area; and adjusting, in accordance with correlations between the macros and multiple registers, the macros in the floor plan.

Abstract: A semiconductor device includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and second transistors operate under a lower gate voltage than the third and fourth transistors. The first transistor has a first active gate structure and the second transistor has a second active gate structure. The first and second active gate structures are separated by a first gate isolation structure along a first direction. The third transistor has a third active gate structure and the fourth transistor has a fourth active gate structure. The third and fourth active gate structures are separated by a second gate isolation structure along the first direction. The variation of a first distance between respective sidewalls of the first gate isolation structure is equal to the variation of a second distance between respective sidewalls of the second gate isolation structure along the first direction.

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

Abstract: A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

Abstract: A sputtering target comprising a sputtering material and having a non-planar sputtering surface prior to erosion by use in a sputtering system, the non-planar sputtering surface having a circular shape and comprising a central axis region including a concave curvature feature at the central axis region. The central axis region having a wear profile after erosion by use in a sputtering system for at least 1000 kWhrs including a protuberance including a first outer circumferential wear surface having a first slope. A reference, protruding convex curvature feature for a reference target after sputtering use for the same time includes a second outer circumferential wear surface having a second slope. The protuberance provides a sputtered target having reduced shadowing relative to the reference, protruding convex curvature feature, wherein the first slope is less steep than a second slope.

Abstract: In an embodiment, a device includes: an isolation region; nanostructures protruding above a top surface of the isolation region; a gate structure wrapped around the nanostructures, the gate structure having a bottom surface contacting the isolation region, the bottom surface of the gate structure extending away from the nanostructures a first distance, the gate structure having a sidewall disposed a second distance from the nanostructures, the first distance less than or equal to the second distance; and a hybrid fin on the sidewall of the gate structure.

Abstract: The present disclosure discloses a portable electronic device including a primary display panel, a keyboard module, a secondary display panel, and a support plate. The primary display panel includes a first pivot and a second pivot. The first pivot and the second pivot are disposed at the primary display panel. The keyboard module faces the primary display panel and includes a third pivot. One side of the secondary display panel is connected to the first pivot, and another side is a free side. The secondary display panel is flipped through the first pivot to be overlapped on an upper surface of the keyboard module or to abut against the upper surface at the free side. The support plate is flipped through the second pivot and the third pivot to be overlapped on the bottom surface of the primary display panel or to support the primary display panel.

Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.

Abstract: A method, computer program, and computer system is provided for estimating three-dimensional hand poses in images. Data corresponding to two hand images is receive, and an optical flow value corresponding to a change in a hand gesture in the received hand image data is calculate. A heat map is generated based on the calculated optical flow, and a hand mesh map is estimated based on the generated heat map. A hand pose present within the hand images is determined based on the estimated hand mesh map.